SCn_DAT

SCn_RXTOUT

SCn_ETUCTL

SCn_INTEN

SCn_INTSTS

SCn_STATUS

SCn_PINCTL

SCn_TMRCTL0

SCn_TMRCTL1

SCn_TMRCTL2

SCn_UARTCTL

SCn_CTL

SCn_ACTCTL

SCn_ALTCTL

SCn_EGT

DAT : Receive/Transmit Holding Buffer \nWrite Operation:\nBy writing data to DAT, the SC will send out an 8-bit data.\nNote: If SCEN(SC_CTL[0]) is not enabled, DAT cannot be programmed.\nRead Operation:\nBy reading DAT, the SC will return an 8-bit received data.
bits : 0 - 7 (8 bit)
access : read-write

RFTM : SC Receiver FIFO Time-out \nNote1:The counter unit is ETU based and the interval of time-out is RFTM + 0.5.\nNote2: Filling in all 0 to this field indicates to disable this function.
bits : 0 - 8 (9 bit)
access : read-write

ETURDIV : ETU Rate Divider\nThe field indicates the clock rate divider.\nThe real ETU is ETURDIV + 1.\nNote: Software can configure this field, but this field must be greater than 0x004.
bits : 0 - 11 (12 bit)
access : read-write

RDAIEN : Receive Data Reach Interrupt Enable Bit\nThis field is used to enable received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TBEIEN : Transmit Buffer Empty Interrupt Enable Bit\nThis field is used to enable transmit buffer empty interrupt.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TERRIEN : Transfer Error Interrupt Enable Bit\nThis field is used to enable transfer error interrupt. The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5]), parity error PEF(SC_STATUS[4]), receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOV(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22]) and transmitter retry over limit error TXOVERR (SC_STATUS[30]).
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0IEN : Timer0 Interrupt Enable Bit\nThis field is used to enable TMR0 interrupt.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1IEN : Timer1 Interrupt Enable Bit\nThis field is used to enable the TMR1 interrupt.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR2IEN : Timer2 Interrupt Enable Bit\nThis field is used to enable TMR2 interrupt.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BGTIEN : Block Guard Time Interrupt Enable Bit\nThis field is used to enable block guard time interrupt.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CDIEN : Card Detect Interrupt Enable Bit\nThis field is used to enable card detect interrupt. The card detect status is CINSERT(SC_STATUS[12])
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INITIEN : Initial End Interrupt Enable Bit
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXTOEN : Receiver Buffer Time-out Interrupt Enable Bit\nThis field is used to enable receiver buffer time-out interrupt.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACERRIEN : Auto Convention Error Interrupt Enable Bit\nThis field is used to enable auto-convention error interrupt.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RDAIF : Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt status flag.\nNote: This field is the status flag of received data reaching RXTRGLV (SC_CTL[7:6]). If software reads data from SC_DAT and receiver buffer data byte number is less than RXTRGLV (SC_CTL[7:6]), this bit will be cleared automatically.
bits : 0 - 0 (1 bit)
access : read-only

TBEIF : Transmit Buffer Empty Interrupt Status Flag (Read Only)\nThis field is used for transmit buffer empty interrupt status flag.\nNote: This field is the status flag of transmit buffer empty state. If software wants to clear this bit, software must write data to DAT(SC_DAT[7:0]) buffer and then this bit will be cleared automatically.
bits : 1 - 1 (1 bit)
access : read-only

TERRIF : Transfer Error Interrupt Status Flag (Read Only)\nThis field is used for transfer error interrupt status flag. The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5], parity error PEF(SC_STATUS[4] and receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOV(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22] and transmitter retry over limit error TXOVERR(SC_STATUS[30]).\nNote: This field is the status flag of BEF(SC_STATUS[6]), FEF(SC_STATUS[5]), PEF(SC_STATUS[4]), RXOV(SC_STATUS[0]), TXOV(SC_STATUS[8]), RXOVERR(SC_STATUS[22]) or TXOVERR(SC_STATUS[30]). So, if software wants to clear this bit, software must write 1 to each field.
bits : 2 - 2 (1 bit)
access : read-only

TMR0IF : Timer0 Interrupt Status Flag (Read Only)\nThis field is used for TMR0 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
bits : 3 - 3 (1 bit)
access : read-only

TMR1IF : Timer1 Interrupt Status Flag (Read Only)\nThis field is used for TMR1 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
bits : 4 - 4 (1 bit)
access : read-only

TMR2IF : Timer2 Interrupt Status Flag (Read Only)\nThis field is used for TMR2 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
bits : 5 - 5 (1 bit)
access : read-only

BGTIF : Block Guard Time Interrupt Status Flag (Read Only) This field is used for block guard time interrupt status flag. Note1: This bit is valid when RXBGTEN (SC_ALTCTL[12]) is enabled. Note2: This bit is read only, but it can be cleared by writing 1 to it.
bits : 6 - 6 (1 bit)
access : read-only

CDIF : Card Detect Interrupt Status Flag (Read Only)\nThis field is used for card detect interrupt status flag. The card detect status is CINSERT (SC_STATUS[12]) and CREMOVE(SC_STATUS[11]).\nNote: This field is the status flag of CINSERT(SC_STATUS[12]) or CREMOVE(SC_STATUS[11])]. So if software wants to clear these bits, software must write 1 to these field.
bits : 7 - 7 (1 bit)
access : read-only

INITIF : Initial End Interrupt Status Flag (Read Only)\nThis field is used for activation (ACTEN(SC_ALTCTL[3])), deactivation (DACTEN (SC_ALTCTL[2])) and warm reset (WARSTEN (SC_ALTCTL[4])) sequence interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
bits : 8 - 8 (1 bit)
access : read-only

RBTOIF : Receiver Buffer Time-out Interrupt Status Flag (Read Only)\nThis field is used for receiver buffer time-out interrupt status flag.\nNote: This field is the status flag of receiver buffer time-out state. If software wants to clear this bit, software must read all receiver buffer remaining data by reading SC_DAT buffer,
bits : 9 - 9 (1 bit)
access : read-only

ACERRIF : Auto Convention Error Interrupt Status Flag (Read Only)\nThis field indicates auto convention sequence error. If the received TS at ATR state is neither 0x3B nor 0x3F, this bit will be set.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
bits : 10 - 10 (1 bit)
access : read-only

RXOV : RX Overflow Error Status Flag (Read Only)\nThis bit is set when RX buffer overflow.\nIf the number of received bytes is greater than Rx Buffer size (4 bytes), this bit will be set.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-only

RXEMPTY : Receiver Buffer Empty Status Flag(Read Only)\nThis bit indicates RX buffer empty or not.\nWhen the last byte of Rx buffer has been read by CPU, hardware sets this bit high. It will be cleared when SC receives any new data.
bits : 1 - 1 (1 bit)
access : read-only

RXFULL : Receiver Buffer Full Status Flag (Read Only)\nThis bit indicates RX buffer full or not.\nThis bit is set when RX pointer is equal to 4, otherwise it is cleared by hardware.
bits : 2 - 2 (1 bit)
access : read-only

PEF : Receiver Parity Error Status Flag (Read Only) This bit is set to logic 1 whenever the received character does not have a valid parity bit . Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
bits : 4 - 4 (1 bit)
access : read-only

FEF : Receiver Frame Error Status Flag (Read Only) This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0). Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
bits : 5 - 5 (1 bit)
access : read-only

BEF : Receiver Break Error Status Flag (Read Only) This bit is set to logic 1 whenever the received data input (RX) held in the spacing state (logic 0) is longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). . Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
bits : 6 - 6 (1 bit)
access : read-only

TXOV : TX Overflow Error Interrupt Status Flag (Read Only) If TX buffer is full, an additional write to DAT(SC_DAT[7:0]) will cause this bit be set to 1 by hardware. Note: This bit is read only, but it can be cleared by writing 1 to it.
bits : 8 - 8 (1 bit)
access : read-only

TXEMPTY : Transmit Buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer empty or not.\nWhen the last byte of TX buffer has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into DAT(SC_DAT[7:0]) (TX buffer not empty).
bits : 9 - 9 (1 bit)
access : read-only

TXFULL : Transmit Buffer Full Status Flag (Read Only)\nThis bit indicates TX buffer full or not.This bit is set when TX pointer is equal to 4, otherwise is cleared by hardware.
bits : 10 - 10 (1 bit)
access : read-only

RXPOINT : Receiver Buffer Pointer Status Flag (Read Only)\nThis field indicates the RX buffer pointer status flag. When SC receives one byte from external device, RXPOINT(SC_STATUS[17:16]) increases one. When one byte of RX buffer is read by CPU, RXPOINT(SC_STATUS[17:16]) decreases one.
bits : 16 - 17 (2 bit)
access : read-only

RXRERR : Receiver Retry Error (Read Only)\nThis bit is set by hardware when RX has any error and retries transfer.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU.\nNote3: If CPU enables receiver retry function by setting RXRTYEN (SC_CTL[19]) , the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])).
bits : 21 - 21 (1 bit)
access : read-only

RXOVERR : Receiver over Retry Error (Read Only)\nThis bit is set by hardware when RX transfer error retry over retry number limit.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2: If CPU enables receiver retries function by setting RXRTYEN (SC_CTL[19]), the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])).
bits : 22 - 22 (1 bit)
access : read-only

RXACT : Receiver in Active Status Flag (Read Only)\nThis bit is set by hardware when RX transfer is in active.\nThis bit is cleared automatically when RX transfer is finished.
bits : 23 - 23 (1 bit)
access : read-only

TXPOINT : Transmit Buffer Pointer Status Flag (Read Only)\nThis field indicates the TX buffer pointer status flag. When CPU writes data into SC_DAT, TXPOINT increases one. When one byte of TX Buffer is transferred to transmitter shift register, TXPOINT decreases one.
bits : 24 - 25 (2 bit)
access : read-only

TXRERR : Transmitter Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU.
bits : 29 - 29 (1 bit)
access : read-only

TXOVERR : Transmitter over Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits over retry number limitation.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
bits : 30 - 30 (1 bit)
access : read-only

TXACT : Transmit in Active Status Flag (Read Only)
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PWREN : SC_PWREN Pin Signal\nSoftware can set PWREN (SC_PINCTL[0]) and PWRINV (SC_PINCTL[11])to decide SC_PWR pin is in high or low level.\nWrite this field to drive SC_PWR pin\nRefer PWRINV (SC_PINCTL[11]) description for programming SC_PWR pin voltage level.\nRead this field to get SC_PWR pin status.\nNote: When operating at hardware activation, warm reset or deactivation mode, this bit will be changed automatically. Thus,do not fill in this field when operating in these modes.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCRST : SC_RST Pin Signal\nThis bit is the pin status of SC_RST but user can drive SC_RST pin to high or low by setting this bit.\nWrite this field to drive SC_RST pin.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. Thus,do not fill in this field when operating in these modes.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CREMOVE : Card Detect Removal Status of SC_CD Pin (Read Only) This bit is set whenever card has been removal. Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2: Card detect engine will start after SCEN (SC_CTL[0])set.
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CINSERT : Card Detect Insert Status of SC_CD Pin (Read Only) This bit is set whenever card has been inserted. Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2: Thecard detect engine will start after SCEN (SC_CTL[0]) set.
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CDPINSTS : Card Detect Status of SC_CD Pin Status (Read Only)\nThis bit is the pin status flag of SC_CD
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CLKKEEP : SC Clock Enable Bit \nNote: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically. Thus,do not fill in this field when operating in these modes.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADACEN : Auto Deactivation When Card Removal\nNote: When the card is removed, hardware will stop any process and then do deactivation sequence (if this bit is set). If this process completes, hardware will generate an interrupt INITIF to CPU.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCDOUT : SC Data Output Pin \nThis bit is the pin status of SCDATOUT but user can drive SCDATOUT pin to high or low by setting this bit.\nNote: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically. Thus,do not fill in this field when SC is in these modes.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CDLV : Card Detect Level\ndetected. \nNote: Software must select card detect level before Smart Card engine is enabled.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWRINV : SC_POW Pin Inverse\nThis bit is used for inverse the SC_POW pin.\nThere are four kinds of combination for SC_POW pin setting by PWRINV(SC_PINCTL[11]) and PWREN(SC_PINCTL[0]). PWRINV (SC_PINCTL[11]) is bit 1 and PWREN(SC_PINCTL[0]) is bit 0 for SC_POW_Pin as high or low voltage selection.\nNote:Software must select PWRINV (SC_PINCTL[11]) before Smart Card is enabled by SCEN (SC_CTL[0]).
bits : 11 - 11 (1 bit)
access : read-write

DATSTS : SC Data Input Pin Status (Read Only)\nThis bit is the pin status of SC_DAT
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SYNC : SYNC Flag Indicator(Read Only)\nDue to synchronization, software should check this bit when writing a new value to SC_PINCTL register.
bits : 30 - 30 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CNT : Timer 0 Counter Value (ETU Based)\nThis field indicates the internal timer operation values.
bits : 0 - 23 (24 bit)
access : read-write

OPMODE : Timer 0 Operation Mode Selection\nThis field indicates the internal 24-bit timer operation selection.\nRefer toTable6.153TimerOperation Modefor programming Timer0.
bits : 24 - 27 (4 bit)
access : read-write

SYNC : SYNC Flag Indicator(Read Only)\nDue to synchronization, software should check this bit when writing a new value to the SC_TMRCTL0 register.
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CNT : Timer 1 Counter Value (ETU Based)\nThis field indicates the internal timer operation values.
bits : 0 - 7 (8 bit)
access : read-write

OPMODE : Timer 1 Operation Mode Selection\nThis field indicates the internal 8-bit timer operation selection.\nRefer toTable6.153TimerOperation Modefor programming Timer1.
bits : 24 - 27 (4 bit)
access : read-write

SYNC : SYNC Flag Indicator(Read Only)\nDue to synchronization, software should check this bit when writing a new value to the SC_TMRCTL1 register.
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CNT : Timer 2 Counter Value (ETU Based)\nThis field indicates the internal timer operation values.
bits : 0 - 7 (8 bit)
access : read-write

OPMODE : Timer 2 Operation Mode Selection\nThis field indicates the internal 8-bit timer operation selection\nRefer to Table6.153TimerOperation Modefor programming Timer2.
bits : 24 - 27 (4 bit)
access : read-write

SYNC : SYNC Flag Indicator(Read Only)\nDue to synchronization, software should check this bit when writing a new value to SC_TMRCTL2 register.
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

UARTEN : UART Mode Enable Bit\nNote3: When UART is enabled, hardware will generate a resetto reset FIFO and internal state machine.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WLS : Word Length Selection\nNote: In smart card mode, this WLS must be '00'
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PBOFF : Parity Bit Disable Control\nNote: In smart card mode, this field must be '0' (default setting is with parity bit)
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OPE : Odd Parity Enable Bit\nNote: This bit has effect only when PBOFF bit is '0'.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCEN : SC Engine Enable Bit\nSet this bit to 1 to enable SC operation. If this bit is cleared, SC will force all transition to IDLE state\nNote1: SCEN must be set to 1 before filling in other registers, or smart card will not work properly.\nNote2: If SCEN is activated, all function can work correctly. If SCEN is not activated, when CPU write data to SMC, only Flip-flop which works in PCLK domain will turn on for two PCLK cycle, Flip-flop working in SCLK domain will not be turn on.
bits : 0 - 0 (1 bit)
access : read-write

RXOFF : RX Transition Disable Bit\nNote1: If AUTOCEN (SC_CTL[3])is enabled, these fields must be ignored.\nNote2: After hardware activation and hardware warm reset are done, RXOFF is set to 0 automatically.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXOFF : TX Transition Disable Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AUTOCEN : Auto Convention Enable Bit
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CONSEL : Convention Selection\nNote: If AUTOCEN(SC_CTL[3]) is enabled, this field is ignored.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXTRGLV : Rx Buffer Trigger Level \nWhen the number of bytes in the receiving buffer equals the RXTRGLV, the RDAIF will be set (if SC_INTEN [RDAIEN] is enabled, an interrupt will be generated).
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BGT : Block Guard Time (BGT)\nNote: The real block guard time is BGT + 1.
bits : 8 - 12 (5 bit)
access : read-write

TMRSEL : Timer Selection \nOther configurations are reserved
bits : 13 - 14 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

NSB : Stop Bit Length\nThis field indicates the length of stop bit.\nNote: The default stop bit length is 2. SMC and UART adopt NSB to program the stop bit length.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXRTY : RX Error Retry Count Number\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred\nNote1: The real retry number is RX_ERETRY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when RX_ERETRY_EN enabled. The change flow is to disable RX_ETRTRY_EN first and then fill in new retry value.
bits : 16 - 18 (3 bit)
access : read-write

RXRTYEN : RX Error Retry Enable Bit\nThis bit enables receiver retry function when parity error has occurred.\nNote: Software must fill in the RXRTY value before enabling this bit.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXRTY : TX Error Retry Count Number\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote1: The real retry number is TXRTY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when TXRTYEN enabled. The change flow is to disable TXRTYEN first and then fill in new retry value.
bits : 20 - 22 (3 bit)
access : read-write

TXRTYEN : TX Error Retry Enable Bit\nThis bit enables transmitter retry function when parity error has occurred.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CDDBSEL : Card Detect De-bounce Selection\nThis field indicates the card detect de-bounce selection.\nOther configurations are reserved.
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SYNC : SYNC Flag Indicator(Read Only)\nDue to synchronization, software should check this bit before writing a new value to RXRTY and TXRTY.SYNC delay is
bits : 30 - 30 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

T1EXT : Configurable Cycles T1EXT in Hardware Activation \nThis field provide the configurable cycles to extend the Activation time T1\nThe cycle scaling factor is 2048.\nNote: setting 0 to this field conforms to the protocol ISO/IEC 7816-3
bits : 0 - 4 (5 bit)
access : read-write

TXRST : TX Software Reset\nWhen TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXRST : Rx Software Reset\nWhen RXRST is set, all the bytes in the receiver buffer and Rx internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DACTEN : Deactivation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by deactivation sequence\nNote1: When the deactivation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by TXRST (SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).Thus,do not fill in this bit, TXRST, and RXRST at the same time.\nNote3: If SCEN (SC_CTL[0]) is not enabled, this filed cannot be programmed.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACTEN : Activation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by activation sequence\nNote1: When the activation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1, RXOFF(SC_CTL[2]) will be clear to 0.\nNote2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).Thus,do not fill in this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.\nNote3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WARSTEN : Warm Reset Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by warm reset sequence\nNote1: When the warm reset sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1, RXOFF(SC_CTL[2]) will be clear to 0.\nNote2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).Thus,do not fill in this bit, TXRST, and RXRST at the same time.\nNote3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTEN0 : Internal Timer0 Start Enable Bit\nThis bit enables Timer 0 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTEN1 : Internal Timer1 Start Enable Bit\nThis bit enables Timer 1 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTEN2 : Internal Timer2 Start Enable Bit\nThis bit enables Timer 2 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INITSEL : Initial Timing Selection\nThis fields indicates the timing of hardware initial state (activation or warm-reset or deactivation).\nUnit: SC clock\nActivation: Refer to SC Activation Sequence in Figure 6.154SC Activation Sequence.\nWarm-reset: Refer to Warm-Reset Sequence in Figure 6.155SC Warm Reset Sequence\nDeactivation: Refer to Deactivation Sequence in Figure 6.156SC Deactivation Sequence\nNote: When set Activation and Warm reset in mode 11, it may have deviation at most 128 cycles.
bits : 8 - 9 (2 bit)
access : read-write

RXBGTEN : Receiver Block Guard Time Function Enable Bit
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACTSTS0 : Internal Timer0 Active State (Read Only)\nThis bit indicates the timer counter status of timer0.\nNote: Timer0 is active does not always mean timer0 is counting the CNT(SC_TMRCTL0[23:0]).
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ACTSTS1 : Internal Timer1 Active State (Read Only)\nThis bit indicates the timer counter status of timer1.\nNote: Timer1 is active does not always mean timer1 is counting the CNT(SC_TMRCTL1[7:0]).
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ACTSTS2 : Internal Timer2 Active State (Read Only)\nThis bit indicates the timer counter status of timer2.\nNote: Timer2 is active does not always mean timer2 is counting the CNT(SC_TMRCTL2[7:0]).
bits : 15 - 15 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

OUTSEL : Smartcard Data Pin Output Mode Selection\nUse this bit to select smartcard data pin output mode.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EGT : Extra Guard Time\nThis field indicates the extra guard timer value.\nNote: The counter is ETU base .
bits : 0 - 7 (8 bit)
access : read-write