\n
address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
Analog Comparator 0 Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACMPEN : Comparator Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Comparator 0 Disabled
#1 : 1
Comparator 0 Enabled
End of enumeration elements list.
ACMPIE : Comparator Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Comparator 0 interrupt Disabled
#1 : 1
Comparator 0 interrupt Enabled. If WKEN (ACMP_CTL0[31]) is set to 1, the wake-up interrupt function will be enabled as well
End of enumeration elements list.
HYSEN : Comparator Hysteresis Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Comparator 0 hysteresis Disabled
#1 : 1
Comparator 0 hysteresis Enabled
End of enumeration elements list.
NEGSEL : Comparator Negative Input Selection
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
ACMP0_N pin
#01 : 1
Internal comparator reference voltage (CRV)
#10 : 2
Internal reference voltage (Int_VREF)
#11 : 3
AVSS pin
End of enumeration elements list.
WKEN : Power-down Wake-up Enable Bit
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Wake-up function Disabled
#1 : 1
Wake-up function Enabled
End of enumeration elements list.
Analog Comparator Status Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACMPIF : ComparatorInterrupt Flag
This bit is set by hardware whenever the comparator 0 output changes state. This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1
Note: Write 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write
ACMPO : ComparatorOutput\nSynchronized to the PCLK to allow reading by software. Cleared when the comparator 0 is disabled, i.e. ACMPEN (ACMP_CTL0[0]) is cleared to 0.\nNote: This bit is read only.
bits : 1 - 1 (1 bit)
access : read-write
Analog Comparator Reference Voltage Control Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRVCTL : Comparator Reference Voltage Setting
bits : 0 - 3 (4 bit)
access : read-write
CRVEN : CRV Enable Bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
CRV Disabled
#1 : 1
CRV Enabled
End of enumeration elements list.
CRVSSEL : CRV Source Voltage Selection
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
VDDA is selected as CRV source voltage
#1 : 1
The reference voltage defined by SYS_VREFCTL register is selected as CRV source voltage
End of enumeration elements list.
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