\n
address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x100 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x80 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x30 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x60 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
Part Device Identification Number Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PDID : Part Device ID \nThis register reflects device part number code. Software can read this register to identify which device is used.
bits : 0 - 31 (32 bit)
access : read-only
Register Lock Key Address
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RegUnLock : Protected Register Enable Control\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Protected register are Locked. Any write to the target register is ignored
#1 : 1
Protected registers are Unlocked
End of enumeration elements list.
Temperature Sensor Control Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTEMP_EN : Temperature Sensor Enable Control\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Temperature sensor function Disabled (default)
#1 : 1
Temperature sensor function Enabled
End of enumeration elements list.
Port A Low Byte Multiple Function Control Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA0_MFP : PA.0 Pin Function Selection\n
bits : 0 - 3 (4 bit)
access : read-write
PA1_MFP : PA.1 Pin Function Selection\n
bits : 4 - 7 (4 bit)
access : read-write
PA2_MFP : PA.2 Pin Function Selection\n
bits : 8 - 11 (4 bit)
access : read-write
PA3_MFP : PA.3 Pin Function Selection\n
bits : 12 - 15 (4 bit)
access : read-write
PA4_MFP : PA.4 Pin Function Selection\n
bits : 16 - 19 (4 bit)
access : read-write
PA5_MFP : PA.5 Pin Function Selection\n
bits : 20 - 23 (4 bit)
access : read-write
PA6_MFP : PA.6 Pin Function Selection\n
bits : 24 - 27 (4 bit)
access : read-write
PA7_MFP : PA.7 Pin Function Selection\n
bits : 28 - 31 (4 bit)
access : read-write
Port A High Byte Multiple Function Control Register
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA8_MFP : PA.8 Pin Function Selection\n
bits : 0 - 3 (4 bit)
access : read-write
PA9_MFP : PA.9 Pin Function Selection\n
bits : 4 - 7 (4 bit)
access : read-write
PA10_MFP : PA.10 Pin Function Selection\n
bits : 8 - 11 (4 bit)
access : read-write
PA11_MFP : PA.11 Pin Function Selection\n
bits : 12 - 15 (4 bit)
access : read-write
PA12_MFP : PA.12 Pin Function Selection\n
bits : 16 - 19 (4 bit)
access : read-write
PA13_MFP : PA.13 Pin Function Selection\n
bits : 20 - 23 (4 bit)
access : read-write
PA14_MFP : PA.14 Pin Function Selection\n
bits : 24 - 27 (4 bit)
access : read-write
PA15_MFP : PA.15 Pin Function Selection\n
bits : 28 - 31 (4 bit)
access : read-write
Port B Low Byte Multiple Function Control Register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PB0_MFP : PB.0 Pin Function Selection\n
bits : 0 - 3 (4 bit)
access : read-write
PB1_MFP : PB.1 Pin Function Selection\n
bits : 4 - 7 (4 bit)
access : read-write
PB2_MFP : PB.2 Pin Function Selection\n
bits : 8 - 11 (4 bit)
access : read-write
PB3_MFP : PB.3 Pin Function Selection\n
bits : 12 - 15 (4 bit)
access : read-write
PB4_MFP : PB.4 Pin Function Selection\n
bits : 16 - 19 (4 bit)
access : read-write
PB5_MFP : PB.5 Pin Function Selection\n
bits : 20 - 23 (4 bit)
access : read-write
PB6_MFP : PB.6 Pin Function Selection\n
bits : 24 - 27 (4 bit)
access : read-write
PB7_MFP : PB.7 Pin Function Selection\n
bits : 28 - 31 (4 bit)
access : read-write
Port B High Byte Multiple Function Control Register
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PB8_MFP : PB.8 Pin Function Selection\n
bits : 0 - 3 (4 bit)
access : read-write
PB9_MFP : PB.9 Pin Function Selection\n
bits : 4 - 7 (4 bit)
access : read-write
PB10_MFP : PB.10 Pin Function Selection\n
bits : 8 - 11 (4 bit)
access : read-write
PB11_MFP : PB.11 Pin Function Selection\n
bits : 12 - 15 (4 bit)
access : read-write
PB12_MFP : PB.12 Pin Function Selection\n
bits : 16 - 19 (4 bit)
access : read-write
PB13_MFP : PB.13 Pin Function Selection\n
bits : 20 - 23 (4 bit)
access : read-write
PB14_MFP : PB.14 Pin Function Selection\n
bits : 24 - 27 (4 bit)
access : read-write
PB15_MFP : PB.15 Pin Function Selection\n
bits : 28 - 31 (4 bit)
access : read-write
System Reset Source Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSTS_POR : The RSTS_POR Flag Is Set by the Reset Signal From the Power-on Reset (POR) Module or Bit CHIP_RST (IPRSTC1[0]) to Indicate the Previous Reset Source
Note: This bit is cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from POR or CHIP_RST
#1 : 1
Power-on Reset (POR) or CHIP_RST had issued the reset signal to reset the system
End of enumeration elements list.
RSTS_PAD : The RSTS_PAD Flag Is Set by the Reset Signal From the /RESET Pin or Power Related Reset Sources to Indicate the Previous Reset Source
Note: This bit is cleared by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from nRESET pin
#1 : 1
The /RESET pin had issued the reset signal to reset the system
End of enumeration elements list.
RSTS_WDT : The RSTS_WDT Flag Is Set by the Reset Signal From the Watchdog Timer Module to Indicate the Previous Reset Source
Note: This bit is cleared by writing 1 to it.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from Watchdog Timer
#1 : 1
The Watchdog Timer module had issued the reset signal to reset the system
End of enumeration elements list.
RSTS_BOD : The RSTS_BOD Flag Is Set by the Reset Signal From the Brown-out-detected Module to Indicate the Previous Reset Source
Note: This bit is cleared by writing 1 to it.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from BOD
#1 : 1
Brown-out-Detected module had issued the reset signal to reset the system
End of enumeration elements list.
RSTS_SYS : The RSTS_SYS Flag Is Set by the Reset Signal From the Cortex_M0 Kernel to Indicate the Previous Reset Source
Note: This bit is cleared by writing 1 to it.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from Cortex_M0
#1 : 1
Cortex_M0 had issued the reset signal to reset the system by writing 1 to the bit SYSRESTREQ(AIRCR[2], Application Interrupt and Reset Control Register) in system control registers of Cortex_M0 kernel
End of enumeration elements list.
RSTS_CPU : The RSTS_CPU Flag Is Set by Hardware If Software Writes CPU_RST (IPRST_CTL1[1]) 1 to Rest Cortex-m0 Core and Flash Memory Controller (FMC)
Note: This bit is cleared by writing 1 to it.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from CPU
#1 : 1
Cortex-M0 core and FMC are reset by software setting CPU_RST to 1
End of enumeration elements list.
Port C Low Byte Multiple Function Control Register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PC0_MFP : PC.0 Pin Function Selection\n
bits : 0 - 3 (4 bit)
access : read-write
PC1_MFP : PC.1 Pin Function Selection\n
bits : 4 - 7 (4 bit)
access : read-write
PC2_MFP : PC.2 Pin Function Selection\n
bits : 8 - 11 (4 bit)
access : read-write
PC3_MFP : PC.3 Pin Function Selection\n
bits : 12 - 15 (4 bit)
access : read-write
PC4_MFP : PC.4 Pin Function Selection\n
bits : 16 - 19 (4 bit)
access : read-write
PC5_MFP : PC.5 Pin Function Selection\n
bits : 20 - 23 (4 bit)
access : read-write
PC6_MFP : PC.6 Pin Fuction Selection\n
bits : 24 - 27 (4 bit)
access : read-write
PC7_MFP : PC.7 Pin Function Selection\n
bits : 28 - 31 (4 bit)
access : read-write
Port C High Byte Multiple Function Control Register
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PC8_MFP : PC.8 Pin Function Selection\n
bits : 0 - 3 (4 bit)
access : read-write
PC9_MFP : PC.9 Pin Function Selection\n
bits : 4 - 7 (4 bit)
access : read-write
PC10_MFP : PC.10 Pin Function Selection\n
bits : 8 - 11 (4 bit)
access : read-write
PC11_MFP : PC.11 Pin Function Selection\n
bits : 12 - 15 (4 bit)
access : read-write
PC12_MFP : PC.12 Pin Function Selection\n
bits : 16 - 19 (4 bit)
access : read-write
PC13_MFP : PC.13 Pin Function Selection\n
bits : 20 - 23 (4 bit)
access : read-write
PC14_MFP : PC.14 Pin Function Selection\n
bits : 24 - 27 (4 bit)
access : read-write
PC15_MFP : PC.15 Pin Function Selection\n
bits : 28 - 31 (4 bit)
access : read-write
Port D Low Byte Multiple Function Control Register
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD0_MFP : PD.0 Pin Function Selection\n
bits : 0 - 3 (4 bit)
access : read-write
PD1_MFP : PD.1 Pin Function Selection\n
bits : 4 - 7 (4 bit)
access : read-write
PD2_MFP : PD.2 Pin Function Selection\n
bits : 8 - 11 (4 bit)
access : read-write
PD3_MFP : PD.3 Pin Function Selection\n
bits : 12 - 15 (4 bit)
access : read-write
PD4_MFP : PD.4 Pin Function Selection\n
bits : 16 - 19 (4 bit)
access : read-write
PD5_MFP : PD.5 Pin Function Selection\n
bits : 20 - 23 (4 bit)
access : read-write
PD6_MFP : PD.6 Pin Function Selection\n
bits : 24 - 27 (4 bit)
access : read-write
PD7_MFP : PD.7 Pin Function Selection\n
bits : 28 - 31 (4 bit)
access : read-write
Port D High Byte Multiple Function Control Register
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD8_MFP : PD.8 Pin Function Selection\n
bits : 0 - 3 (4 bit)
access : read-write
PD9_MFP : PD.9 Pin Function Selection\n
bits : 4 - 7 (4 bit)
access : read-write
PD10_MFP : PD.10 Pin Function Selection\n
bits : 8 - 11 (4 bit)
access : read-write
PD11_MFP : PD.11 Pin Function Selection\n
bits : 12 - 15 (4 bit)
access : read-write
PD12_MFP : PD.12 Pin Function Selection\n
bits : 16 - 19 (4 bit)
access : read-write
PD13_MFP : PD.13 Pin Function Selection\n
bits : 20 - 23 (4 bit)
access : read-write
PD14_MFP : PD.14 Pin Function Selection\n
bits : 24 - 27 (4 bit)
access : read-write
PD15_MFP : PD.15 Pin Function Selection\n
bits : 28 - 30 (3 bit)
access : read-write
Port E Low Byte Multiple Function Control Register
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PE0_MFP : PE.0 Pin Function Selection\n
bits : 0 - 3 (4 bit)
access : read-write
PE1_MFP : PE.1 Pin Function Selection\n
bits : 4 - 7 (4 bit)
access : read-write
PE2_MFP : PE.2 Pin Function Selection\n
bits : 8 - 11 (4 bit)
access : read-write
PE3_MFP : PE.3 Pin Function Selection\n
bits : 12 - 15 (4 bit)
access : read-write
PE4_MFP : PE.4 Pin Function Selection\n
bits : 16 - 19 (4 bit)
access : read-write
PE5_MFP : PE.5 Pin Function Selection\n
bits : 20 - 23 (4 bit)
access : read-write
PE6_MFP : PE.6 Pin Function Selection\n
bits : 24 - 27 (4 bit)
access : read-write
PE7_MFP : PE.7 Pin Function Selection\n
bits : 28 - 31 (4 bit)
access : read-write
Port E High Byte Multiple Function Control Register
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PE8_MFP : PE.8 Pin Function Selection\n
bits : 0 - 3 (4 bit)
access : read-write
PE9_MFP : PE.9 Pin Function Selection\n
bits : 4 - 7 (4 bit)
access : read-write
Port F Low Byte Multiple Function Control Register
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PF0_MFP : PF.0 Pin Function Selection\n
bits : 0 - 3 (4 bit)
access : read-write
PF1_MFP : PF.1 Pin Function Selection\n
bits : 4 - 7 (4 bit)
access : read-write
PF2_MFP : PF.2 Pin Function Selection\n
bits : 8 - 11 (4 bit)
access : read-write
PF3_MFP : PF.3 Pin Function Selection\n\n
bits : 12 - 15 (4 bit)
access : read-write
PF4_MFP : PF.4 Pin Function Selection\n
bits : 16 - 19 (4 bit)
access : read-write
PF5_MFP : PF.5 Pin Function Selection\n
bits : 20 - 23 (4 bit)
access : read-write
Power-On-reset Controller Register
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POR_DIS_CODE : Power-on Reset Enable Control
This is a protected register. Please refer to open lock sequence to program it.
When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. If setting the POR_DIS_CODE to 0x5AA5, the POR reset function will be disabled and the POR function will be active again when POR_DIS_CODE is set to another value or POR_DIS_CODE is reset by chip other reset functions, including: /RESET, Watchdog Timer reset, BOD reset, ICE reset command and the software-chip reset function
bits : 0 - 15 (16 bit)
access : read-write
Brown-out Detector Controller Register
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOD17_EN : Brown-out Detector 1.7V Function Enable Control\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brown-out Detector 1.7V function Disabled
#1 : 1
Brown-out Detector 1.7V function Enabled
End of enumeration elements list.
BOD20_EN : Brown-out Detector 2.0 V Function Enable Control\nThis is a protected register. Please refer to open lock sequence to program it.\nBOD20_EN is default on. If SW disables it, Brown-out Detector 2.0 V function is not disabled until chip enters Power-down mode. If system is not in Power-down mode, BOD20_EN will be enabled by hardware automatically.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brown-out Detector 2.0 V function Disabled
#1 : 1
Brown-out Detector 2.0 V function Enabled
End of enumeration elements list.
BOD25_EN : Brown-out Detector 2.5 V Function Enable Control\nThis is a protected register. Please refer to open lock sequence to program it.\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brown-out Detector 2.5 V function Disabled
#1 : 1
Brown-out Detector 2.5 V function Enabled
End of enumeration elements list.
BOD17_RST_EN : BOD 1.7 V Reset Enable Control\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reset does not issue when BOD17 occurs
#1 : 1
Reset issues when BOD17 occurs
End of enumeration elements list.
BOD20_RST_EN : BOD 2.0 V Reset Enable Control\nThis is a protected register. Please refer to open lock sequence to program it.\nThe default value is set by flash controller user configuration register config0 bit[20:19]
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reset does not issue when BOD20 occurs
#1 : 1
Reset issues when BOD20 occurs
End of enumeration elements list.
BOD25_RST_EN : BOD 2.5 V Reset Enable Control\nThis is a protected register. Please refer to open lock sequence to program it.\nThe default value is set by flash controller user configuration register config0 bit[20:19]
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reset does not issue when BOD25 occurs
#1 : 1
Reset issues when BOD25 occurs
End of enumeration elements list.
BOD17_INT_EN : BOD 1.7 V Interrupt Enable Control\nThis is a protected register. Please refer to open lock sequence to program it.\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt does not issue when BOD17 occurs
#1 : 1
Interrupt issues when BOD17 occurs
End of enumeration elements list.
BOD20_INT_EN : BOD 2.0 V Interrupt Enable Control\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt does not issue when BOD20 occurs
#1 : 1
Interrupt issues when BOD20 occurs
End of enumeration elements list.
BOD25_INT_EN : BOD 2.5 V Interrupt Enable Control\nThis is a protected register. Please refer to open lock sequence to program it.\n
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt does not issue when BOD25 occurs
#1 : 1
Interrupt issues when BOD25 occurs
End of enumeration elements list.
BOD17_TRIM : BOD 1.7 TRIM Value
This is a protected register. Please refer to open lock sequence to program it.
This value is used to control BOD17 detect voltage level, nominal 1.7 V. Higher trim value, higher detection voltage.
bits : 12 - 15 (4 bit)
access : read-write
BOD20_TRIM : BOD 2.0 TRIM Value
This is a protected register. Please refer to open lock sequence to program it.
This value is used to control BOD20 detect voltage level, nominal 2.0 V. Higher trim value, higher detection voltage.
bits : 16 - 19 (4 bit)
access : read-write
BOD25_TRIM : BOD 2.5 TRIM Value
This is a protected register. Please refer to open lock sequence to program it.
This value is used to control BOD25 detect voltage level, nominal 2.5 V. Higher trim value, higher detection voltage.
bits : 20 - 23 (4 bit)
access : read-write
Brown-out Detector Status Register
address_offset : 0x68 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BOD_INT : Brown-out Detector Interrupt Status\nThis bit is cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Brown-out Detector does not detect any voltage drift at VDD down through or up through the target detected voltage after interrupt is enabled
#1 : 1
When Brown-out Detector detects the VDD is dropped down through the target detected voltage or the VDD is raised up through the target detected voltage and Brown-out interrupt is enabled, this bit will be set to 1
End of enumeration elements list.
BOD17_drop : Brown-out Detector Lower Than 1.7V Status\nSetting BOD17_drop high means once the detected voltage is lower than target detected voltage setting (1.7V). Software can write 1 to clear BOD17_drop
bits : 1 - 1 (1 bit)
access : read-only
BOD20_drop : Brown-out Detector Lower Than 2.0V Status\nSetting BOD20_drop high means once the detected voltage is lower than target detected voltage setting (2.0V). Software can write 1 to clear BOD20_drop
bits : 2 - 2 (1 bit)
access : read-only
BOD25_drop : Brown-out Detector Lower Than 2.5V Status\nSetting BOD25_drop high means once the detected voltage is lower than target detected voltage setting (2.5V). Software can write 1 to clear BOD25_drop
bits : 3 - 3 (1 bit)
access : read-only
BOD17_rise : Brown-out Detector Higher Than 1.7V Status\nSetting BOD17_rise high means once the detected voltage is higher than target detected voltage setting (1.7V). Software can write 1 to clear BOD17_rise
bits : 4 - 4 (1 bit)
access : read-only
BOD20_rise : Brown-out Detector Higher Than 2.0V Status\nSetting BOD20_rise high means once the detected voltage is higher than target detected voltage setting (2.0V). Software can write 1 to clear BOD20_rise
bits : 5 - 5 (1 bit)
access : read-only
BOD25_rise : Brown-out Detector Higher Than 2.5V Status\nSetting BOD25_rise high means once the detected voltage is higher than target detected voltage setting (2.5V). Software can write 1 to clear BOD25_rise.
bits : 6 - 6 (1 bit)
access : read-only
BOD17 : Brown-out Detector 1.7V Status\nThis bit reflects the BOD17 status. BOD17 is high if detected voltage is higher than 1.7 V. BOD17 is low if detected voltage is lower than 1.7 V.\nNote: This bit is ready-only.
bits : 8 - 8 (1 bit)
access : read-only
BOD20 : Brown-out Detector 2.0V Status\nThis bit reflects the BOD20 status. BOD20 is high if detected voltage is higher than 2.0 V. BOD20 is low if detected voltage is lower than 2.0 V.\nNote: This bit is ready-only.
bits : 9 - 9 (1 bit)
access : read-only
BOD25 : Brown-out Detector 2.5V Status\nThis bit reflects the BOD25 status. BOD25 is high if detected voltage is higher than 2.5 V. BOD25 is low if detected voltage is lower than 2.5 V.\nNote: This bit is ready-only.
bits : 10 - 10 (1 bit)
access : read-only
Internal Voltage Reference Control Register
address_offset : 0x6C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BGP_EN : Band-gap Enable Control\nThis is a protected register. Please refer to open lock sequence to program it.\nBand-gap is the reference voltage of internal reference voltage. User must enable band-gap if want to enable internal 1.5, 1.8V or 2.5V reference voltage.\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
REG_EN : Regulator Enable Control\nEnable internal 1.5, 1.8V or 2.5V reference voltage.\nThis is a protected register. Please refer to open lock sequence to program it.\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
SEL25 : Regulator Output Voltage Selection\nSelect internal reference voltage level.\nThis is a protected register. Please refer to open lock sequence to program it.\n
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
1.5V
#01 : 1
1.8V
#10 : 2
2.5V
#11 : 3
2.5V
End of enumeration elements list.
EXT_MODE : Regulator External Mode\nThis is a protected register. Please refer to open lock sequence to program it.\nUsers can output regulator output voltage in VREF pin if EXT_MODE is high.\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No connection with external VREF pin
#1 : 1
Connet to external VREF pin. Connect a 1uF to 10uF capacitor to AVSS will let internal voltage reference be more stable
End of enumeration elements list.
VREF_TRIM : Internal Voltage Reference Trim
bits : 8 - 11 (4 bit)
access : read-write
LDO Control Register
address_offset : 0x70 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LDO_PD : LDO Power Off\nThis is a protected register. Please refer to open lock sequence to program it.\nSet this bit high will off LDO and cause Chip in unexpected state. User must keep this bit low. \n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
LDO Enabled
#1 : 1
LDO Disabled
End of enumeration elements list.
LDO_LEVEL : LDO Output Voltage Select
This is a protected register. Please refer to open lock sequence to program it.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Reseved
#01 : 1
1.6V
#10 : 2
1.8V
#11 : 3
1.8V
End of enumeration elements list.
Peripheral Reset Control Resister1
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHIP_RST : Chip One-shot Reset
This is a protected register. Please refer to open lock sequence to program it.
Setting this bit will reset the whole chip, including Cortex-M0 core and all peripherals like power-on reset and this bit will automatically return to 0 after the 2 clock cycles.
The chip setting from flash will be also reloaded when chip one shot reset.
Note: In the following conditions, chip setting from flash will be reloaded.
Power-on Reset
Brown-out-Detected Reset
Low level on the nRESET pin
Set IPRST_CTL1[CHIP_RST]
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal
#1 : 1
Reset chip
End of enumeration elements list.
CPU_RST : Cortex-m0 Core One-shot Reset
This is a protected register. Please refer to open lock sequence to program it.
Setting this bit will only reset the Cortex-M0 core and Flash Memory Controller (FMC), and this bit will automatically return to 0 after the 2 clock cycles
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal
#1 : 1
Reset Cortex-M0 core
End of enumeration elements list.
DMA_RST : DMA Controller Reset
This is a protected register. Please refer to open lock sequence to program it.
Set this bit 1 will generate a reset signal to the DMA. SW needs to set this bit to low to release reset signal.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation
#1 : 1
DMA IP reset
End of enumeration elements list.
HIRC Trim Control Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIM_SEL : Trim Frequency Selection\n
bits : 0 - 1 (2 bit)
access : read-write
TRIM_LOOP : Trim Calculation Loop\n
bits : 4 - 5 (2 bit)
access : read-write
TRIM_RETRY_CNT : Trim Value Update Limitation Count\n
bits : 6 - 7 (2 bit)
access : read-write
ERR_STOP : Trim Stop When 32.768 KHz Error Detected\nThis bit is used to control if stop the HIRC trim operation when 32.768 kHz clock error is detected.\nIf set this bit high and 32.768 kHz clock error detected, the status 32K_ERR_INT (IRCTRIMINT[2]) would be set high and HIRC trim operation was stopped. If this bit is low and 32.768 kHz clock error detected, the status 32K_ERR_INT (IRCTRIMINT[2]) would be set high and HIRC trim operation is continuously.\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Continue the HIRC trim operation even if 32.768 kHz clock error detected
#1 : 1
Stop the HIRC trim operation if 32.768 kHz clock error detected
End of enumeration elements list.
HIRC Trim Interrupt Enable Register
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIM_FAIL_IEN : Trim Failure Interrupt Enable Control\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by TRIM_SEL (IRCTRIMCTL[1:0]).\nIf this bit is high and TRIM_FAIL_INT (IRCTRIMINT[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
TRIM_FAIL_INT (IRCTRIMINT[1:0]) status Disabled to trigger an interrupt to CPU
#1 : 1
TRIM_FAIL_INT (IRCTRIMINT[1:0]) status Enabled to trigger an interrupt to CPU
End of enumeration elements list.
_32K_ERR_IEN : 32.768 KHz Clock Error Interrupt Enable Control\nThis bit controls if CPU would get an interrupt while 32.768 kHz clock is inaccuracy during auto trim operation.\nIf this bit is high, and 32K_ERR_INT (IRCTRIMINT[2]) is set during auto trim operation, an interrupt will be triggered to notify the 32.768 kHz clock frequency is inaccuracy.\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
32K_ERR_INT (IRCTRIMINT[2]) status Disabled to trigger an interrupt to CPU
#1 : 1
32K_ERR_INT (IRCTRIMINT[2]) status Enabled to trigger an interrupt to CPU
End of enumeration elements list.
HIRC Trim Interrupt Status Register
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQ_LOCK : HIRC Frequency Lock Status\nThis bit indicates the HIRC frequency lock.\nThis is a status bit and doesn't trigger any interrupt.
bits : 0 - 0 (1 bit)
access : read-write
TRIM_FAIL_INT : Trim Failure Interrupt Status\nThis bit indicates that HIRC trim value update limitation count reached and HIRC clock frequency still doesn't lock. Once this bit is set, the auto trim operation stopped and TRIM_SEL (IRCTRIMCTL[1:0]) will be cleared to 00 by hardware automatically.\nIf this bit is set and TRIM_FAIL_IEN (IRCTRIMIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. Write 1 to clear this to zero.\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Trim value update limitation count doesn't reach
#1 : 1
Trim value update limitation count reached and HIRC frequency still doesn't lock
End of enumeration elements list.
_32K_ERR_INT : 32.768 KHz Clock Error Interrupt Status\nThis bit indicates that 32.768 kHz clock frequency is inaccuracy. Once this bit is set, the auto trim operation stopped and TRIM_SEL (IRCTRIMCTL[1:0]) will be cleared to 00 by hardware automatically.\nIf this bit is set and 32K_ERR_IEN (IRCTRIMIEN[2]) is high, an interrupt will be triggered to notify the 32.768 kHz clock frequency is inaccuracy. Write 1 to clear this to zero.\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
32.768 kHz clock frequency is accuracy
#1 : 1
32.768 kHz clock frequency is inaccuracy
End of enumeration elements list.
Peripheral Reset Control Resister2
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO_RST : GPIO Controller Reset\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO module normal operation
#1 : 1
GPIO module reset
End of enumeration elements list.
TMR0_RST : Timer0 Controller Reset\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer0 module normal operation
#1 : 1
Timer0 module reset
End of enumeration elements list.
TMR1_RST : Timer1 Controller Reset\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer1 module normal operation
#1 : 1
Timer1 module reset
End of enumeration elements list.
TMR2_RST : Timer2 Controller Reset\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer2 module normal operation
#1 : 1
Timer2 module reset
End of enumeration elements list.
TMR3_RST : Timer3 Controller Reset\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer3 module normal operation
#1 : 1
Timer3 module reset
End of enumeration elements list.
I2C0_RST : I2C0 Controller Reset\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C0 module normal operation
#1 : 1
I2C0 module reset
End of enumeration elements list.
I2C1_RST : I2C1 Controller Reset\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C1 module normal operation
#1 : 1
I2C1 module reset
End of enumeration elements list.
SPI0_RST : SPI0 Controller Reset\n
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI0 module normal operation
#1 : 1
SPI0 module reset
End of enumeration elements list.
SPI1_RST : SPI1 Controller Reset\n
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI1 module normal operation
#1 : 1
SPI1 module reset
End of enumeration elements list.
UART0_RST : UART0 Controller Reset\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART0 module normal operation
#1 : 1
UART0 module reset
End of enumeration elements list.
UART1_RST : UART1 Controller Reset\n
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART1 module normal operation
#1 : 1
UART1 module reset
End of enumeration elements list.
PWM0_RST : PWM0 Controller Reset\n
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM0 module normal operation
#1 : 1
PWM0 module reset
End of enumeration elements list.
ACMP01_RST : Comparator Controller Reset\n
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Comparator module normal operation
#1 : 1
Comparator module reset
End of enumeration elements list.
LCD_RST : LCD Controller Reset\n
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
LCD module normal operation
#1 : 1
LCD module reset
End of enumeration elements list.
ADC_RST : ADC Controller Reset\n
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
ADC module normal operation
#1 : 1
ADC module reset
End of enumeration elements list.
SC0_RST : SmartCard 0 Controller Reset\n
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
SmartCard module normal operation
#1 : 1
SmartCard module reset
End of enumeration elements list.
SC1_RST : SmartCard1 Controller Reset\n
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
SmartCard module normal operation
#1 : 1
SmartCard module reset
End of enumeration elements list.
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