PWRCTL

CLKSEL0

CLKSEL1

CLKSEL2

CLKDIV0

CLKDIV1

PLLCTL

FRQDIV0

WK_INTSTS

APB_DIV

FRQDIV1

CLK_SP_DET (SP_DET)

AHBCLK

CLK_SP_STS (SP_STS)

APBCLK

CLKSTATUS

HXT_EN : HXT Enable Control\nThis is a protected register. Please refer to open lock sequence to program it.\nThe bit default value is set by flash controller user configuration register config0 [26].\nHXT is disabled by default.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LXT_EN : LXT Enable Control\nThis is a protected register. Please refer to open lock sequence to program it.\nLXT is disabled by default.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HIRC_EN : HIRC Enable Control\nThis is a protected register. Please refer to open lock sequence to program it.\nHIRC is enabled by default.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LIRC_EN : LIRC Enable Control\nThis is a protected register. Please refer to open lock sequence to program it.\nLIRC is enabled by default.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WK_DLY : Wake-up Delay Counter Enable Control\nThis is a protected register. Please refer to open lock sequence to program it.\nWhen chip wakes up from Power-down mode, the clock control will delay 4096 clock cycles to wait HXT stable or 16 clock cycles to wait HIRC stable.\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PD_WK_IE : Power-down Mode Wake-up Interrupt Enable Control\nThis is a protected register. Please refer to open lock sequence to program it.\nPD_WK_INT will be set if both PD_WK_IS and PD_WK_IE are high.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PD_EN : Chip Power-down Mode Enable Bit This is a protected register. Please refer to open lock sequence to program it. When CPU sets this bit, the chip power down is enabled and chip will not enter Power-down mode until CPU sleep mode is also active. When chip wakes up from Power-down mode, this bit will be auto cleared. When chip is in Power-down mode, the LDO, HXT and HIRC will be disabled, but LXT and LIRC are not controlled by Power-down mode. When power down, the PLL and system clock (CPU, HCLKx and PCLKx) are also disabled no matter the Clock Source selection. Peripheral clocks are not controlled by this bit, if peripheral Clock Source is from LXT or LIRC. In Power-down mode, flash macro power is ON.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HXT_SELXT : HXT SELXT\nThis is a protected register. Please refer to open lock sequence to program it.\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HXT_CUR_SEL : HXT Internal Current Selection HXT has some internal current path to help crystal start-up. However when these currnet path existence, HXT will consume more power. User can use this bit to balance the start-up and power consumption. For 4 MHz to 16 MHz crystal.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HXT_GAIN : HXT Gain Control Bit\nThis is a protected register. Please refer to open lock sequence to program it.\nGain control is used to enlarge the gain of crystal to make sure crystal wok normally. If gain control is enabled, crystal will consume more power than gain control off. \n
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HIRC_FSEL : HIRC Output Frequency Select\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HIRC_F_STOP : HIRC Stop Output When Frequency Changes This is a protected register. Please refer to open lock sequence to program it.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HCLK_S : HCLK Clock Source Selection\n
bits : 0 - 2 (3 bit)
access : read-write

UART_S : UART 0/1 Clock Source Selection (UART0 and UART1 Use the Same Clock Source Selection)\n
bits : 0 - 1 (2 bit)
access : read-write

PWM0_CH01_S : PWM0 Channel 0 and Channel 1 Clock Source Selection\n
bits : 4 - 5 (2 bit)
access : read-write

PWM0_CH23_S : PWM0 Channel 2 and Channel 3 Clock Source Selection\n
bits : 6 - 7 (2 bit)
access : read-write

TMR0_S : Timer0 Clock Source Selection\n\n
bits : 8 - 10 (3 bit)
access : read-write

TMR1_S : Timer1 Clock Source Selection\n
bits : 12 - 14 (3 bit)
access : read-write

LCD_S : LCD Clock Source Selection
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADC_S : ADC Clock Source Selection\n
bits : 19 - 21 (3 bit)
access : read-write

FRQDIV1_S : Clock Divider Clock1 Source Selection\n
bits : 0 - 1 (2 bit)
access : read-write

FRQDIV0_S : Clock Divider0 Clock Source Selection\n
bits : 2 - 3 (2 bit)
access : read-write

TMR2_S : Timer2 Clock Source Selection\n
bits : 8 - 10 (3 bit)
access : read-write

TMR3_S : Timer3 Clock Source Selection\n
bits : 12 - 14 (3 bit)
access : read-write

SC_S : SC Clock Source Selection\n
bits : 18 - 19 (2 bit)
access : read-write

SPI0_S : SPI0 Clock Source Selection\n
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI1_S : SPI1 Clock Source Selection\n
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HCLK_N : HCLK Clock Divide Number From HCLK Clock Source\n
bits : 0 - 3 (4 bit)
access : read-write

UART_N : UART Clock Divide Number From UART Clock Source\n
bits : 8 - 11 (4 bit)
access : read-write

ADC_N : ADC Clock Divide Number From ADC Clock Source\n
bits : 16 - 23 (8 bit)
access : read-write

SC0_N : SC 0 Clock Divide Number From SC 0 Clock Source\n
bits : 28 - 31 (4 bit)
access : read-write

SC1_N : SC 1 Clock Divide Number From SC 1 Clock Source\n
bits : 0 - 3 (4 bit)
access : read-write

TMR0_N : Timer0 Clock Divide Number From Timer0 Clock Source\n
bits : 8 - 11 (4 bit)
access : read-write

TMR1_N : Timer1 Clock Divide Number From Timer1 Clock Source\n
bits : 12 - 15 (4 bit)
access : read-write

TMR2_N : Timer2 Clock Divide Number From Timer2 Clock Source\n
bits : 16 - 19 (4 bit)
access : read-write

TMR3_N : Timer3 Clock Divide Number From Timer3 Clock Source\n
bits : 20 - 23 (4 bit)
access : read-write

PLL_MLP : PLL Multiple 000000: Reserved 000001: X1 000010: X2 000011: X3 000100: X4 ... 010000:X16 ... 100000: X32 0thers: Reserved PLL output frequency: PLL input frequency * PLL_MLP. PLL output frequency range: 16MHz ~ 32MHz
bits : 0 - 5 (6 bit)
access : read-write

PLL_SRC_N : PLL Input Source Divider PLL input clock frequency range: 0.8MHz ~ 2MHz
bits : 8 - 11 (4 bit)
access : read-write

PD : Power-down Mode If set the PD_EN bit 1 in PWR_CTL register, the PLL will enter Power-down mode too
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PLL_SRC : PLL Source Clock Select\n
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FSEL : Divider Output Frequency Selection Bits\nThe formula of output frequency is\nWhere FRQDIV0_CLK is the input clock frequency, Fout is the frequency of divider output clock and N is the 4-bit value of FSEL[3:0].
bits : 0 - 3 (4 bit)
access : read-write

FDIV_EN : Frequency Divider Enable Bit\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DIV1 : Output Frequency Divied by 1\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PD_WK_IS : Wake-up Interrupt Sstatus in Chip Power-down Mode\nThis bit indicates that some event resumes chip from Power-down mode \nThe status is set if external interrupts, UART, GPIO, RTC, USB, SPI, Timer, WDT, and BOD wake-up occurred.\nWrite 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-only

APBDIV : APB Clock Divider\nAPB PCLK can be divided from HCLK.\n
bits : 0 - 2 (3 bit)
access : read-write

FSEL : Divider Output Frequency Selection Bits\nThe formula of output frequency is\nWhere FRQDIV1_CLK is the input clock frequency, Fout is the frequency of divider output clock and N is the 4-bit value of FSEL[3:0].
bits : 0 - 3 (4 bit)
access : read-write

FDIV_EN : Frequency Divider Enable Bit\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DIV1 : Output Frequency Divied by 1\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HCLK_DET : HCLK Stop Detect Enable Control\nOnce HCLK stop detected, hardware will force HCLK from LIRC.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HCLK_DET_IE : HCLK Stop Detect Interrupt Enable Control\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HXT_DET : HXT Stop Detect Enable Control\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HXT_STOP_IE : HXT Stop Detect Interrupt Enable Control\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HIRC_DET : HIRC Stop Detect Enable Control\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HIRC_STOP_IE : HIRC Stop Detect Interrupt Enable Control\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPIO_EN : GPIO Controller Clock Enable Control\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMA_EN : DMA Controller Clock Enable Control\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISP_EN : Flash ISP Controller Clock Enable Control\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SRAM_EN : SRAM Controller Clock Enable Control\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TICK_EN : System Tick Clock Enable Control\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HCLK_SP_IS : HCLK Clock Stop Flag\n
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

HXT_SP_IS : HXT Stop Flag\n
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

HIRC_SP_IS : HIRC Stop Flag\n
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

H_TCLK_SEL : HCLK Target Clock Select\n
bits : 8 - 10 (3 bit)
access : read-only

WDT_EN : Watchdog Timer Clock Enable Control \nThis is a protected register. Please refer to open lock sequence to program it.\nThis bit is used to control the WDT APB clock only, The WDT engine Clock Source is from LIRC.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTC_EN : Real-time-clock Clock Enable Control \nThis bit is used to control the RTC APB clock only, The RTC engine Clock Source is from LXT.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0_EN : Timer0 Clock Enable Control\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1_EN : Timer1 Clock Enable Control\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR2_EN : Timer2 Clock Enable Control\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR3_EN : Timer3 Clock Enable Control\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FDIV0_EN : Frequency Divider0 Output Clock Enable Control\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FDIV1_EN : Frequency Divider1 Output Clock Enable Control\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C0_EN : I2C0 Clock Enable Control \n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C1_EN : I2C1 Clock Enable Control \n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACMP_EN : ACMP Clock Enable Control \n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI0_EN : SPI0 Clock Enable Control \n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI1_EN : SPI1 Clock Enable Control \n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART0_EN : UART0 Clock Enable Control\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART1_EN : UART1 Clock Enable Control\n
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM0_CH01_EN : PWM0 Channel 0 and Channel 1Clock Enable Control\n
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM0_CH23_EN : PWM0 Channel 2 and Channel 3 Clock Enable Control\n
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LCD_EN : LCD Controller Clock Enable Control\n
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADC_EN : Analog-digital-converter (ADC) Clock Enable Control\n
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SC0_EN : SmartCard 0 Clock Enable Control\n
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SC1_EN : SmartCard 1 Clock Enable Control\n
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HXT_STB : HXT Clock Source Stable Flag\n
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

LXT_STB : LXT Clock Source Stable Flag\n
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PLL_STB : PLL Clock Source Stable Flag\n
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

LIRC_STB : LIRC Clock Source Stable Flag\n
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

HIRC_STB : HIRC Clock Source Stable Flag\n
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CLK_SW_FAIL : Clock Switch Fail Flag\nThis bit will be set when target switch Clock Source is not stable. This bit is write 1 clear
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.