ISPCON

ISPTRG

DFBADR

ISPADR

ISPSTA

ISPDAT

ISPCMD

ISPEN : ISP Enable Control (Write Protect)\nISP function enable bit. Set this bit to enable ISP function.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BS : Boot Select (Write Protect) Set/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS in Config0 after power-on reset It keeps the same value at other reset.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

APUEN : APROM Update Enable Control (Write Protect)\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFGUEN : Enable Config-bits Update by ISP (Write Protect)\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LDUEN : LDROM Update Enable Control (Write Protect)\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISPFF : ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(3) User Configuration is erased/programmed when CFGUEN is 0.\n(4) Destination address is illegal, such as over an available range.\nNote: Write 1 to clear this bit to 0.
bits : 6 - 6 (1 bit)
access : read-write

ISPGO : ISP Start Trigger\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DFBADR : Data Flash Base Address\nThis register indicates data flash start address. It is a read only register.\nThe data flash start address is defined by user. Since on chip flash erase unit is 512 bytes, it is mandatory to keep bit 8-0 as 0.
bits : 0 - 31 (32 bit)
access : read-only

ISPADR : ISP Address\nThis chip supports word program only. ISPADR[1:0] must be kept 00b for ISP operation, and ISPADR[8:0] must be kept all 0 for Vector Page Re-map Command
bits : 0 - 31 (32 bit)
access : read-write

ISPBUSY : ISP Busy (Read Only)\n
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CBS : Config Boot Selection Status (Read Only)\nThis filed is a mirror of CBS in CONFIG0.
bits : 1 - 2 (2 bit)
access : read-only

PGFF : Auto Flash Program Verified Fail Flag This chip will perform flash verification automatically at the end of ISP PROGRAM operation, and set 1 to this bit when flash data is not matched with programming. This bit is clear to 0 by ERASE command.
bits : 5 - 5 (1 bit)
access : read-write

ISPFF : ISP Fail Flag\n(3) User Configuration is erased/programmed when CFGUEN is 0.\n(4) Destination address is illegal, such as over an available range.\nNote: Write 1 to clear this bit to 0.
bits : 6 - 6 (1 bit)
access : read-write

VECMAP : Vector Page Mapping Address (Read Only) The current system memory space 0x0000_0000~0x0000_01FF is mapped to flash memory page with base address (VECMAP[11:0] 9).
bits : 9 - 20 (12 bit)
access : read-only

ISPDAT : ISP Data\nWrite data to this register before ISP program operation\nRead data from this register after ISP read operation
bits : 0 - 31 (32 bit)
access : read-write

FCTRL : ISP Command\nThe ISP command table is shown as follows.
bits : 0 - 3 (4 bit)
access : read-write

FCEN : ISP Command\nThe ISP command table is shown as follows.
bits : 4 - 4 (1 bit)
access : read-write

FOEN : ISP Command\nThe ISP command table is shown as follows.
bits : 5 - 5 (1 bit)
access : read-write