\n

PDMA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected

Registers

DMA_GCRCSR

DMA_DSSR0

DMA_DSSR1

DMA_GCRISR


DMA_GCRCSR

DMA Global Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_GCRCSR DMA_GCRCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLK1_EN CLK2_EN CLK3_EN CLK4_EN CRC_CLK_EN

CLK1_EN : PDMA Controller Channel 1 Clock Enable Control\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

CLK2_EN : PDMA Controller Channel 2 Clock Enable Control \n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

CLK3_EN : PDMA Controller Channel 3 Clock Enable Control\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

CLK4_EN : PDMA Controller Channel 4 Clock Enable Control\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

CRC_CLK_EN : CRC Controller Clock Enable Control\n
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.


DMA_DSSR0

DMA Service Selection Control Register 0
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_DSSR0 DMA_DSSR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH1_SEL CH2_SEL CH3_SEL

CH1_SEL : Channel 1 Selection \nThis filed defines which peripheral is connected to PDMA channel 1. User can configure the peripheral by setting CH1_SEL.\n
bits : 8 - 12 (5 bit)
access : read-write

Enumeration:

#00000 : 0

Connect to SPI0_TX

#00001 : 1

Connect to SPI1_TX

#00010 : 2

Connect to UART0_TX

#00011 : 3

Connect to UART1_TX

#00100 : 4

Reserved

#00101 : 5

Reserved

#00110 : 6

Reserved

#00111 : 7

Reserved

#01000 : 8

Reserved

#01001 : 9

Connect to TMR0

#01010 : 10

Connect to TMR1

#01011 : 11

Connect to TMR2

#01100 : 12

Connect to TMR3

#10000 : 16

Connect to SPI0_RX

#10001 : 17

Connect to SPI1_RX

#10010 : 18

Connect to UART0_RX

#10011 : 19

Connect to UART1_RX

#10100 : 20

Reserved

#10101 : 21

Reserved

#10110 : 22

Connect to ADC

#10111 : 23

Reserved

#11000 : 24

Reserved

#11001 : 25

Connect to PWM0_CH0

#11010 : 26

Connect to PWM0_CH2

#11011 : 27

Reserved

#11100 : 28

Reserved.

End of enumeration elements list.

CH2_SEL : Channel 2 Selection \nThis filed defines which peripheral is connected to PDMA channel 2. User can configure the peripheral setting by CH2_SEL. The channel configuration is the same as CH1_SEL field. Please refer to the explanation of CH1_SEL.
bits : 16 - 20 (5 bit)
access : read-write

CH3_SEL : Channel 3 Selection \nThis filed defines which peripheral is connected to PDMA channel 3. User can configure the peripheral setting by CH3_SEL. The channel configuration is the same as CH1_SEL field. Please refer to the explanation of CH1_SEL.
bits : 24 - 28 (5 bit)
access : read-write


DMA_DSSR1

DMA Service Selection Control Register 1
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_DSSR1 DMA_DSSR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH4_SEL

CH4_SEL : Channel 4 Selection \nThis filed defines which peripheral is connected to PDMA channel 4. User can configure the peripheral by setting CH4_SEL.\n
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

#00000 : 0

Connect to SPI0_TX

#00001 : 1

Connect to SPI1_TX

#00010 : 2

Connect to UART0_TX

#00011 : 3

Connect to UART1_TX

#00100 : 4

Reserved

#00101 : 5

Reserved

#00110 : 6

Reserved

#00111 : 7

Reserved

#01000 : 8

Reserved

#01001 : 9

Connect to TMR0

#01010 : 10

Connect to TMR1

#01011 : 11

Connect to TMR2

#01100 : 12

Connect to TMR3

#10000 : 16

Connect to SPI0_RX

#10001 : 17

Connect to SPI1_RX

#10010 : 18

Connect to UART0_RX

#10011 : 19

Connect to UART1_RX

#10100 : 20

Reserved

#10101 : 21

Reserved

#10110 : 22

Connect to ADC

#10111 : 23

Reserved

#11000 : 24

Reserved

#11001 : 25

Connect to PWM0_CH0

#11010 : 26

Connect to PWM0_CH2

#11011 : 27

Reserved

#11100 : 28

Reserved

End of enumeration elements list.


DMA_GCRISR

DMA Global Interrupt Status Register
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMA_GCRISR DMA_GCRISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTR1 INTR2 INTR3 INTR4 INTRCRC

INTR1 : Interrupt Status of Channel 1 (Read Only)\nThis bit is the interrupt status of PDMA channel1.
bits : 1 - 1 (1 bit)
access : read-only

INTR2 : Interrupt Status of Channel 2 (Read Only)\nThis bit is the interrupt status of PDMA channel2.\nNote: This bit is read only
bits : 2 - 2 (1 bit)
access : read-only

INTR3 : Interrupt Status of Channel 3 (Read Only)\nThis bit is the interrupt status of PDMA channel3.
bits : 3 - 3 (1 bit)
access : read-only

INTR4 : Interrupt Status of Channel 4 (Read Only)\nThis bit is the interrupt status of PDMA channel4.
bits : 4 - 4 (1 bit)
access : read-only

INTRCRC : Interrupt Status of CRC Controller (Read Only)\nThis bit is the interrupt status of CRC controller
bits : 16 - 16 (1 bit)
access : read-only



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.