TMR1_CTL (CTL)

TMR1_ISR (ISR)

TMR1_DR (DR)

TMR1_TCAP (TCAP)

TMR1_ECTL (ECTL)

TMR1_PRECNT (PRECNT)

TMR1_CMPR (CMPR)

TMR1_IER (IER)

TMR_EN : Timer Counter Enable Control\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SW_RST : Software Reset\nSet this bit will reset the timer counter, pre-scale counter and also force TMR_EN (TMRx_CTL [0]) to 0.\nNote: This bit will be auto cleared and takes at least 3 TMRx_CLK clock cycles.
bits : 1 - 1 (1 bit)
access : read-write

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WAKE_EN : Wake-up Enable Control\nWhen WAKE_EN is set and the TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) is set, the timer controller will generate a wake-up trigger event to CPU.\n
bits : 2 - 2 (1 bit)
access : read-write

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End of enumeration elements list.

DBGACK_EN : ICE Debug Mode Acknowledge Ineffective Enable Control\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

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MODE_SEL : Timer Operating Mode Select\n
bits : 4 - 5 (2 bit)
access : read-write

ACMP_EN_TMR : ACMP Trigger Timer Enable Control\nThis bit high enables the functionality that when ACMP0 is in sigma-delta mode, it could enable Timer.\n
bits : 6 - 6 (1 bit)
access : read-write

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End of enumeration elements list.

TMR_ACT : Timer Active Status Bit (Read Only)\nThis bit indicates the timer counter status of timer.\n
bits : 7 - 7 (1 bit)
access : read-only

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ADC_TEEN : Timer Trigger ADC Enable Control\nThis bit controls if TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) could trigger ADC.\nWhen ADC_TEEN is set, TMR_IS (TMRx_ISR[0]) is set and the CAP_TRG_EN (TMRx_CTL[11]) is low, the timer controller will generate an internal trigger event to ADC controller.\nWhen ADC_TEEN is set, TCAP_IS (TMRx_ISR[1]) is set and the CAP_TRG_EN (TMRx_CTL[11]) is high, the timer controller will generate an internal trigger event to ADC controller.\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDMA_TEEN : Timer Trigger PDMA Enable Control\nThis bit controls if TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) could trigger PDMA.\nWhen PDMA_TEEN is set, TMR_IS (TMRx_ISR[0]) is set and the CAP_TRG_EN (TMRx_CTL[11]) is low, the timer controller will generate an internal trigger event to PDMA controller.\nWhen PDMA_TEEN is set, TCAP_IS (TMRx_ISR[1]) is set and the CAP_TRG_EN (TMRx_CTL[11]) is high, the timer controller will generate an internal trigger event to PDMA controller.\n
bits : 10 - 10 (1 bit)
access : read-write

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End of enumeration elements list.

TMR_TRG_SEL : Timer Trigger Selection\nThis bit controls if the TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) is used to trigger PDMA and ADC while TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) is set.\nIf this bit is low and TMR_IS (TMRx_ISR[0]) is set, timer will generate an internal trigger event to PDMA or ADC while related trigger enable bit (PDMA_TEEN (TMRx_CTL[10]) or ADC_TEEN (TMRx_CTL[8])) is set.\nIf this bit is set high and TCAP_IS (TMRx_ISR[0]) is set, timer will generate an internal trigger event to PDMA or ADC while related trigger enable bit (PDMA_TEEN (TMRx_CTL[10]) or ADC_TEEN (TMRx_CTL[8])) is set.\n
bits : 11 - 11 (1 bit)
access : read-write

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End of enumeration elements list.

EVENT_EN : Event Counting Mode Enable Control\nWhen EVENT_EN is set, the increase of 24-bit up-counting timer is controlled by external event pin.\nWhile the transition of external event pin matches the definition of EVENT_EDGE (TMRx_CTL[13]), the 24-bit up-counting timer increases by 1. Or, the 24-bit up-counting timer will keep its value unchanged.\n
bits : 12 - 12 (1 bit)
access : read-write

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End of enumeration elements list.

EVENT_EDGE : Event Counting Mode Edge Selection\nThis bit indicates which edge of external event pin enabling the timer to increase 1.\n
bits : 13 - 13 (1 bit)
access : read-write

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End of enumeration elements list.

EVNT_DEB_EN : External Event De-bounce Enable Control\nWhen EVNT_DEB_EN is set, the external event pin de-bounce circuit will be enabled to eliminate the bouncing of the signal.\nIn de-bounce circuit the external event pin will be sampled 4 times by TMRx_CLK.\nNote: When EVENT_EN (TMRx_CTL[12]) is enabled, enable this bit is recommended. And, while EVENT_EN (TMRx_CTL[12]) is disabled, disable this bit is recommended to save power consumption.
bits : 14 - 14 (1 bit)
access : read-write

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End of enumeration elements list.

TCAP_EN : TC Pin Functional Enable Control\nThis bit controls if the transition on TC pin could be used as timer counter reset function or timer capture function.\n
bits : 16 - 16 (1 bit)
access : read-write

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End of enumeration elements list.

TCAP_MODE : TC Pin Function Mode Selection\nThis bit indicates if the transition on TC pin is used as timer counter reset function or timer capture function.\n
bits : 17 - 17 (1 bit)
access : read-write

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End of enumeration elements list.

TCAP_EDGE : TC Pin Edge Detect Selection\n
bits : 18 - 19 (2 bit)
access : read-write

TCAP_CNT_MOD : Timer Capture Counting Mode Selection\nThis bit indicates the behavior of 24-bit up-counting timer while TCAP_EN (TMRx_CTL[16]) is set to high.\nIf this bit is 0, the free-counting mode, the behavior of 24-bit up-counting timer is defined by MODE_SEL (TMRx_CTL[5:4]) field. When TCAP_EN (TMRx_CTL[16]) is set, TCAP_MODE (TMRx_CTL[17]) is 0, and the transition of TC pin matches the TCAP_EDGE (TMRx_CTL[19:18]) setting, the value of 24-bit up-counting timer will be saved into register TMRx_TCAP.\nIf this bit is 1, Trigger-counting mode, 24-bit up-counting timer will be not counting and keep its value at 0. When TCAP_EN (TMRx_CTL[16]) is set, TCAP_MODE (TMRx_CTL[17]) is 0, and once the transition of external pin matches the 1st transition of TCAP_EDGE (TMRx_CTL[19:18]) setting, the 24-bit up-counting timer will start counting. And then if the transition of external pin matches the 2nd transition of TCAP_EDGE (TMRx_CTL[19:18]) setting, the 24-bit up-counting timer will stop counting. And its value will be saved into register TMRx_TCAP.\n
bits : 20 - 20 (1 bit)
access : read-write

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End of enumeration elements list.

TCAP_DEB_EN : TC Pin De-bounce Enable Control\nWhen CAP_DEB_EN (TMRx_CTL[22]) is set, the TC pin de-bounce circuit will be enabled to eliminate the bouncing of the signal.\nIn de-bounce circuit the TC pin signal will be sampled 4 times by TMRx_CLK.\nNote: When TCAP_EN (TMRx_CTL[16]) is enabled, enable this bit is recommended. And, while TCAP_EN (TMRx_CTL[16]) is disabled, disable this bit is recommended to save power consumption.\nNote: When CAP_SRC (TMRx_ECTL[16]) is high, the capture signal is from internal of chip and the de-bounce circuit would not take effect no matter this bit is high or low.\nNote: For Timer 1 and 3, when INTR_TRG_EN (TMRx_CTL[24]) is high, the capture signal is from internal of chip and the de-bounce circuit would not take effect no matter this bit is high or low.
bits : 22 - 22 (1 bit)
access : read-write

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End of enumeration elements list.

INTR_TRG_EN : Inter-timer Trigger Function Enable Control\nThis bit controls if Inter-timer Trigger function is enabled.\nIf Inter-timer Trigger function is enabled, the TMRx will be in counter mode and counting with external Clock Source or event. In addition, TMRx+1 will be in trigger-counting mode of capture function.\nNote: For TMRx+1_CTL, this bit is ignored and the read back value is always 0.
bits : 24 - 24 (1 bit)
access : read-write

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End of enumeration elements list.

INTR_TRG_MODE : Inter-timer Trigger Mode Selection\nThis bit controls the timer operation mode when inter-timer trigger function is enabled.\nWhen this bit is low, the TMRx will be in counter mode and counting with external Clock Source or event. In addition, TMRx+1 will be in trigger-counting mode of capture function. In this mode, TMRx_CMPR control when inter-timer trigger function terminated.\nWhen this bit is high, the TMRx will be in counter mode and counting with external Clock Source or event. In addition, TMRx+1 will be in trigger-counting mode of capture function. In this mode, TMRx+1_CMPR control when inter-timer trigger function terminated. In this mode, TMRx would ignore some incoming event based on the EVNT_DROP_CNT (TMRx_ECTL[31:24]). And once the TMRx+1 counter value equal or large than TMRx+1_CMPR, TMRx would terminate the operation when next incoming event received.\nNote: For TMRx+1_CTL, this bit is ignored and the read back value is always 0.
bits : 25 - 25 (1 bit)
access : read-write

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End of enumeration elements list.

TMR_IS : Timer Interrupt Status\nThis bit indicates the interrupt status of Timer.\nThis bit is set by hardware when the up counting value of internal 24-bit counter matches the timer compared value (TMR_CMPR). Write 1 to clear this bit to 0.\nIf this bit is active and TMR_IE (TMRx_IER[0]) is enabled, Timer will trigger an interrupt to CPU.
bits : 0 - 0 (1 bit)
access : read-write

TCAP_IS : Timer Capture Function Interrupt Status\nThis bit indicates the external pin function interrupt status of Timer.\nThis bit is set by hardware when TCAP_EN (TMRx_CTL[16]) is set high, and the transition of external pin matches the TCAP_EDGE (TMRx_CTL[19:18]) setting. Write 1 to clear this bit to 0.\nIf this bit is active and TCAP_IE (TMRx_IER[1]) is enabled, Timer will trigger an interrupt to CPU.
bits : 1 - 1 (1 bit)
access : read-write

TMR_WAKE_STS : Timer Wake-up Status\nIf timer causes CPU wakes up from Power-down mode, this bit will be set to high. It must be cleared by software with a write 1 to this bit.\n
bits : 4 - 4 (1 bit)
access : read-write

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End of enumeration elements list.

NCAP_DET_STS : New Capture Detected Status\nThis status is to indicate there is a new incoming capture event detected before CPU clearing the TCAP_IS (TMRx_ISR[1]) status.\nIf the above condition occurred, the Timer will keep register TMRx_TCAP unchanged and drop the new capture value.\nWrite 1 to clear this bit to 0.\n
bits : 5 - 5 (1 bit)
access : read-write

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TCAP_IS_FEDGE : TC Pin Edge Detect Is Falling\nThis flag indicates the edge detected in TC pin is rising edge or falling edge.\nTimer only updates this flag when it udpates the Timer Capture Data (TMR_TCAP[23:0]) value. When a new incoming capture event detected before CPU clearing the TCAP_IS (TMRx_ISR[1]) status, Timer will keep this bit unchanged.\n
bits : 6 - 6 (1 bit)
access : read-write

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End of enumeration elements list.

TDR : Timer Data Register (Read)\nUser can read this register for internal 24-bit timer up-counter value.\nCounter Reset (Write)\nUser can write any value to this register to reset internal 24-bit timer up-counter and 8-bit pre-scale counter. This reset operation wouldn't affect any other timer control registers and circuit. After reset completed, the 24-bit timer up-counter and 8-bit pre-scale counter restart the counting based on the TMRx_CTL register setting.
bits : 0 - 23 (24 bit)
access : read-write

RSTACT : Reset Active\nThis bit indicates if the counter reset operation active.\nWhen user write this register, timer starts to reset its internal 24-bit timer up-counter and 8-bit pre-scale counter to 0. In the same time, timer set this flag to 1 to indicate the counter reset operation is in progress. Once the counter reset operation done, timer clear this bit to 0 automatically.\nNote: This bit is read only. Write operation wouldn't take any effect.
bits : 31 - 31 (1 bit)
access : read-write

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End of enumeration elements list.

CAP : Timer Capture Data Register\nWhen TCAP_EN (TMRx_CTL[16]) is set, TCAP_MODE (TMRx_CTL[17]) is 0, TCAP_CNT_MOD (TMRx_CTL[20]) is 0, and the transition of external pin matches the TCAP_EDGE (TMRx_CTL[19:18]) setting, the value of 24-bit up-counting timer will be saved into register TMRx_TCAP.\nWhen TCAP_EN (TMRx_CTL[16]) is set, TCAP_MODE (TMRx_CTL[17]) is 0, TCAP_CNT_MOD (TMRx_CTL[20]) is 1, and the transition of external pin matches the 2nd transition of TCAP_EDGE (TMRx_CTL[19:18]) setting, the value of 24-bit up-counting timer will be saved into register TMRx_TCAP.\nUser can read this register to get the counter value.\nWhen a new incoming capture event detected before CPU clearing the TCAP_IS (TMRxISR[1]) status, Timer will keep this filed value unchanged and drop the new capture value.
bits : 0 - 23 (24 bit)
access : read-only

EVNT_GEN_EN : Event Generator Function Enable Control\nWhen this bit is high, timer would generate a high pulse event out when it increases the 24-bit up counter and the polarity of signal defined by EVNT_GEN_SRC (TMRx_ECTL[12]) is same as the polarity defined by EVNT_GEN_POL (TMRx_ECTL[1]).\n
bits : 0 - 0 (1 bit)
access : read-write

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End of enumeration elements list.

EVNT_GEN_POL : Event Generator Reference Input Source Polarity Selection\nWhen this bit is low and EVNT_GEN_EN (TMRx_ECTL[0]) is high, timer would generate a high pulse event out when it increases the 24-bit up counter and the polarity of signal defined by EVNT_GEN_SRC (TMRx_ECTL[12]) is low.\nWhen this bit is high and EVNT_GEN_EN (TMRx_ECTL[0]) is high, timer would generate a low pulse event pulse out when it increases the 24-bit up counter and the polarity of signal defined by EVNT_GEN_SRC (TMRx_ECTL[12]) is high.\nThis bit only affects timer's operation when EVNT_GEN_EN (TMRx_ECTL[0]) is high.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EVNT_CNT_SRC : Event Counting Source Selection\n
bits : 8 - 8 (1 bit)
access : read-write

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End of enumeration elements list.

EVNT_GEN_SRC : Event Generator Reference Input Source Selection\nThis bit defines the event generator function controlled by external event pin or internal event signals from ACMP0.\n
bits : 12 - 12 (1 bit)
access : read-write

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End of enumeration elements list.

CAP_SRC : Capture Function Source Selection\nThis bit defines timer counter reset function or timer capture function controlled by transition of TC pin or transition of internal signals from other functional blocks of this chip.\nNote: When this bit is high, the EVNT_DEB_EN (TMRx_CTL[14]) would not take effect.
bits : 16 - 16 (1 bit)
access : read-write

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End of enumeration elements list.

EVNT_DROP_CNT : Event Drop Count\nThis field indicates timer to drop how many events after inter-timer trigger function enable.\nFor example, if user writes 0x7 to this field, timer would drop 7 first incoming events and starts the inter-timer trigger operation when it get 8th event.\n
bits : 24 - 31 (8 bit)
access : read-write

PRESCALE_CNT : Pre-scale Counter\n
bits : 0 - 7 (8 bit)
access : read-write

TMR_CMP : Timer Compared Value\nTMR_CMP is a 24-bit compared register. When the internal 24-bit up-counter counts and its value is equal to TMR_CMP value, a Timer Interrupt is requested if the timer interrupt is enabled with TMR_EN (TMRx_CTL [0]) is enabled. The TMR_CMP value defines the timer counting cycle time.\nNote1: Never write 0x0 or 0x1 in TMR_CMP, or the core will run into unknown state.\nNote2: No matter TMR_EN (TMRx_CTL [0]) is 0 or 1, whenever software write a new value into this register, TIMER will restart counting using this new value and abort previous count.
bits : 0 - 23 (24 bit)
access : read-write

TMR_IE : Timer Interrupt Enable Control\nNote: If timer interrupt is enabled, the timer asserts its interrupt signal when the associated counter is equal to TMR_CMPR.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TCAP_IE : Timer Capture Function Interrupt Enable Control\nNote: If timer external pin function interrupt is enabled, the timer asserts its interrupt signal when the TCAP_EN (TMRx_CTL[16]) is set and the transition of external pin matches the TCAP_EDGE (TMRx_CTL[19:18]) setting
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.