\n
address_offset : 0x0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x40 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x34 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x28 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1C Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x54 Bytes (0x0)
size : 0x3C byte (0x0)
mem_usage : registers
protection : not protected
PWM Prescaler Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CP01 : Clock Prescaler 0 for PWM Timer 0 1
Clock input is divided by (CP01 + 1) before it is fed to the PWM counter 0 1
bits : 0 - 7 (8 bit)
access : read-write
CP23 : Clock Prescaler 2 for PWM Timer 2 3
Clock input is divided by (CP23 + 1) before it is fed to the PWM counter 2 3
bits : 8 - 15 (8 bit)
access : read-write
DZ01 : Dead Zone Interval Register for CH0 and CH1 Pair\nThese 8 bits determine dead zone length.\nThe unit time of dead zone length is received from clock selector 0.
bits : 16 - 23 (8 bit)
access : read-write
DZ23 : Dead Zone Interval Register for CH2 and CH3 Pair\nThese 8 bits determine dead zone length.\nThe unit time of dead zone length is received from clock selector 2.
bits : 24 - 31 (8 bit)
access : read-write
PWM Interrupt Indication Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMINT0 : PWM Timer 0 Interrupt Flag\nFlag is set by hardware when PWM0 down counter reaches 0, software can clear this bit by writing a one to it.
bits : 0 - 0 (1 bit)
access : read-write
TMINT1 : PWM Timer 1 Interrupt Flag\nFlag is set by hardware when PWM1 down counter reaches 0, software can clear this bit by writing a one to it.
bits : 1 - 1 (1 bit)
access : read-write
TMINT2 : PWM Timer 2 Interrupt Flag\nFlag is set by hardware when PWM2 down counter reaches 0, software can clear this bit by writing a one to it.
bits : 2 - 2 (1 bit)
access : read-write
TMINT3 : PWM Timer 3 Interrupt Flag\nFlag is set by hardware when PWM3 down counter reaches 0, software can clear this bit by writing a one to it.
bits : 3 - 3 (1 bit)
access : read-write
Duty0Syncflag : Duty0 Synchronize Flag\nNote: software should check this flag when writing duty0, if this flag is set, and user ignore this flag and change duty0, the corresponding CNR and CMR may be wrong for one duty cycle
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Duty0 has been synchronized to PWM_CLK domain of channel 0, 1
#1 : 1
Duty0 is synchronizing to PWM_CLK domain of channel 0, 1
End of enumeration elements list.
Duty1Syncflag : Duty1 Synchronize Flag\nNote: software should check this flag when writing duty1, if this flag is set, and user ignore this flag and change duty1, the corresponding CNR and CMR may be wrong for one duty cycle
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Duty1 has been synchronized to PWM_CLK domain of channel 0, 1
#1 : 1
Duty1 is synchronizing to PWM_CLK domain of channel 0, 1
End of enumeration elements list.
Duty2Syncflag : Duty2 Synchronize Flag\nNote: software should check this flag when writing duty2, if this flag is set, and user ignore this flag and change duty2, the corresponding CNR and CMR may be wrong for one duty cycle
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Duty2 has been synchronized to PWM_CLK domain of channel 2, 3
#1 : 1
Duty2 is synchronizing to PWM_CLK domain of channel 2, 3
End of enumeration elements list.
Duty3Syncflag : Duty3 Synchronize Flag\nNote: software should check this flag when writing duty3, if this flag is set, and user ignore this flag and change duty3, the corresponding CNR and CMR may be wrong for one duty cycle
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Duty3 has been synchronized to PWM_CLK domain of channel 2, 3
#1 : 1
Duty3 is synchronizing to PWM_CLK domain of channel 2, 3
End of enumeration elements list.
PresSyncFlag : Prescale Synchronize Flag\nNote: software should check this flag when writing Prescale, if this flag is set, and user ignore this flag and change Prescale, the Prescale may be wrong for one prescale cycle
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Two Prescales have been synchronized to corresponding PWM_CLK (of channel 0,1 or channel 2, 3) domain respectively
#1 : 1
Prescale01 is synchronizing to PWM_CLK domain of channel 0,1 or Prescaler23 is synchronizing to PWM_CLK domain of channel 2, 3
End of enumeration elements list.
PWM Output Enable for PWM0~PWM3
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0_OE : PWM CH0 Output Enable Control\nNote: The corresponding GPI/O pin also must be switched to PWM function (refer to PBx_MFP / PCx_MFP / PDx_MFP)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM CH0 output to pin Disabled
#1 : 1
PWM CH0 output to pin Enabled
End of enumeration elements list.
CH1_OE : PWM CH1 Output Enable Control\nNote: The corresponding GPI/O pin also must be switched to PWM function. (refer to PBx_MFP / PCx_MFP / PDx_MFP)
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM CH1 output to pin Disabled
#1 : 1
PWM CH1 output to pin Enabled
End of enumeration elements list.
CH2_OE : PWM CH2 Output Enable Control R\nNote: The corresponding GPI/O pin also must be switched to PWM function. (refer to PCx_MFP / PDx_MFP / Pex_MFP / PFx_MFP)
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM CH2 output to pin Disabled
#1 : 1
PWM CH2 output to pin Enabled
End of enumeration elements list.
CH3_OE : PWM CH3 Output Enable Control\nNote: The corresponding GPI/O pin also must be switched to PWM function. (refer to PCx_MFP / PDx_MFP / Pex_MFP / PFx_MFP)
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM CH3 output to pin Disabled
#1 : 1
PWM CH3 output to pin Enabled
End of enumeration elements list.
PWM Counter/Comparator Register 0
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CN : PWM Counter/Timer Loaded Value\nCN determines the PWM period.\nIn edge-aligned mode,\nNote: Any write to CN will take effect in next PWM cycle.
bits : 0 - 15 (16 bit)
access : read-write
CM : PWM Comparator Register\nCM determines the PWM duty.\nIn edge-aligned mode,\nNote:Any write to CM will take effect in next PWM cycle.
bits : 16 - 31 (16 bit)
access : read-write
PWM Data Register 0
address_offset : 0x20 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : PWM Data Register\nUser can monitor PWM_DATA to know the current value in 16-bit down count counter of corresponding channel.
bits : 0 - 15 (16 bit)
access : read-only
DATA_H : PWM Data Register \nUser can monitor PWM_DATA to know the current value in 32-bit down count counter of corresponding channel.\nNotes: This will be valid only for the corresponding cascade enable bit is set
bits : 16 - 30 (15 bit)
access : read-only
sync : CN Value Sync with PWM Counter\nNote: when the corresponding cascade enable bit is set, this bit will not appear in the corresponding channel
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
CN value is sync to PWM counter
#1 : 1
CN value is not sync to PWM counter
End of enumeration elements list.
PWM Counter/Comparator Register 1
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Data Register 1
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Counter/Comparator Register 2
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Data Register 2
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Clock Select Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKSEL0 : Timer 0 Clock Source Selection\nSelect clock input for timer 0.\n(Table is the same as CLKSEL3)
bits : 0 - 2 (3 bit)
access : read-write
CLKSEL1 : Timer 1 Clock Source Selection\nSelect clock input for timer 1.\n(Table is the same as CLKSEL3)
bits : 4 - 6 (3 bit)
access : read-write
CLKSEL2 : Timer 2 Clock Source Selection\nSelect clock input for timer 2.\n(Table is the same as CLKSEL3)
bits : 8 - 10 (3 bit)
access : read-write
CLKSEL3 : Timer 3 Clock Source Selection\nSelect clock input for timer 3.\n
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#000 : 0
input clock is divided by 2
#001 : 1
input clock is divided by 4
#010 : 2
input clock is divided by 8
#011 : 3
input clock is divided by 16
#100 : 4
input clock is divided by 1
End of enumeration elements list.
PWM Counter/Comparator Register 3
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Data Register 3
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Capture Control Register
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INV0 : Channel 0 Inverter ON/OFF\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverter OFF
#1 : 1
Inverter ON. Reverse the input signal from GPIO before fed to Capture timer
End of enumeration elements list.
CAPCH0EN : Capture Channel 0 Transition Enable/Disable Control\nWhen Enabled, Capture latched the PWM-timer value and saved to CRL0 (PWM_CRL0[15:0]) for rising latch and CFL0 (PWM_CFL0[15:0]) for falling latch.\nWhen Disabled, Capture does not update CRL0 (PWM_CRL0[15:0]) and CFL0 (PWM_CFL0[15:0]), and disable Channel 0 Interrupt.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture function on channel 0 Disabled
#1 : 1
Capture function on channel 0 Enabled
End of enumeration elements list.
CAPCH0PADEN : Capture Input Enable Control\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the channel 0 input capture signal from corresponding multi-function pin
#1 : 1
Enable the channel 0 input capture signal from corresponding multi-function pin
End of enumeration elements list.
CH0PDMAEN : Channel 0 PDMA Enable Control\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel 0 PDMA function Disabled
#1 : 1
Channel 0 PDMA function Enabled for the channel 0 captured data and transfer to memory
End of enumeration elements list.
PDMACAPMOD0 : Select CRL0 or CFL0 for PDMA Transfer\n
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
reserved
#01 : 1
CRL0 will be transmitted
#10 : 2
CFL0 will be transmitted
#11 : 3
Both CRL0 and CFL0 will be transmitted
End of enumeration elements list.
CAPRELOADREN0 : Reload CNR0 When CH0 Capture Rising Event Comes \n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising capture reload for CH0 Disabled
#1 : 1
Rising capture reload for CH0 Enabled
End of enumeration elements list.
CAPRELOADFEN0 : Reload CNR0 When CH0 Capture Falling Event Comes\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling capture reload for CH0 Disabled
#1 : 1
Falling capture reload for CH0 Enabled
End of enumeration elements list.
INV1 : Channel 1 Inverter ON/OFF\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverter OFF
#1 : 1
Inverter ON. Reverse the input signal from GPIO before fed to Capture timer
End of enumeration elements list.
CAPCH1EN : Capture Channel 1 Transition Enable/Disable Control\nWhen Enabled, Capture latched the PMW-counter and saved to CRL1 (PWM_CRL1[15:0]) for rising latch and CFL1 (PWM_CFL1[15:0]) for falling latch.\nWhen Disabled, Capture does not update CRL1 (PWM_CRL1[15:0]) and CFL1 (PWM_CFL1[15:0]), and disable Channel 1 Interrupt.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture function on channel 1 Disabled
#1 : 1
Capture function on channel 1 Enabled
End of enumeration elements list.
CAPCH1PADEN : Capture Input Enable Control\n
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the channel 1 input capture signal from corresponding multi-function pin
#1 : 1
Enable the channel 1 input capture signal from corresponding multi-function pin
End of enumeration elements list.
CH0RFORDER : None
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM_CFL0 is the first captured data to memory
#1 : 1
PWM_CRL0 is the first captured data to memory
End of enumeration elements list.
CH01CASK : Cascade channel 0 and channel 1 PWM timer for capturing usage
bits : 13 - 13 (1 bit)
access : read-write
CAPRELOADREN1 : Reload CNR1 When CH1 Capture Rising Event Comes\n
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising capture reload for CH1 Disabled
#1 : 1
Rising capture reload for CH1 Enabled
End of enumeration elements list.
CAPRELOADFEN1 : Reload CNR1 When CH1 Capture Falling Event Coming \n
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture falling reload for CH1 Disabled
#1 : 1
Capture falling reload for CH1 Enabled
End of enumeration elements list.
INV2 : Channel 2 Inverter ON/OFF\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverter OFF
#1 : 1
Inverter ON. Reverse the input signal from GPIO before fed to Capture timer
End of enumeration elements list.
CAPCH2EN : Capture Channel 2 Transition Enable/Disable Control\nWhen Enabled, Capture latched the PWM-timer value and saved to CRL2 (PWM_CRL2[15:0]) for rising latch and CFL2 (PWM_CFL2[15:0]) for falling latch.\nWhen Disabled, Capture does not update CRL2 (PWM_CRL2[15:0]) and CFL2 (PWM_CFL2[15:0]), and disable Channel 2 Interrupt.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture function on channel 2 Disabled
#1 : 1
Capture function on channel 2 Enabled
End of enumeration elements list.
CAPCH2PADEN : Capture Input Enable Control\n
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the channel 2 input capture signal from corresponding multi-function pin
#1 : 1
Enable the channel 2 input capture signal from corresponding multi-function pin
End of enumeration elements list.
CH2PDMAEN : Channel 2 PDMA Enable Control\n
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel 2 PDMA function Disabled
#1 : 1
Channel 2 PDMA function Enabled for the channel 2 captured data and transfer to memory
End of enumeration elements list.
PDMACAPMOD2 : Select CRL2 or CFL2 for PDMA Transfer\n
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 0
reserved
#01 : 1
CRL2 will be transmitted
#10 : 2
CFL2 will be transmitted
#11 : 3
Both CRL2 and CFL2 will be transmitted
End of enumeration elements list.
CAPRELOADREN2 : Reload CNR2 When CH2 Capture Rising Event Coming \n
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising capture reload for CH2 Disabled
#1 : 1
Rising capture reload for CH2 Enabled
End of enumeration elements list.
CAPRELOADFEN2 : Reload CNR2 When CH2 Capture Failing Event Coming \n
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Failing capture reload for CH2 Disabled
#1 : 1
Failing capture reload for CH2 Enabled
End of enumeration elements list.
INV3 : Channel 3 Inverter ON/OFF\n
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverter OFF
#1 : 1
Inverter ON. Reverse the input signal from GPIO before fed to Capture timer
End of enumeration elements list.
CAPCH3EN : Capture Channel 3 Transition Enable/Disable Control\nWhen Enabled, Capture latched the PMW-timer and saved to CRL3 (PWM_CRL3[15:0]) for rising latch and CFL3 (PWM_CFL3[15:0]) for falling latch.\nWhen Disabled, Capture does not update CRL3 (PWM_CRL3[15:0]) and CFL3 (PWM_CFL3[15:0]), and disable Channel 3 Interrupt.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture function on channel 3 Disabled
#1 : 1
Capture function on channel 3 Enabled
End of enumeration elements list.
CAPCH3PADEN : Capture Input Enable Control\n
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the channel 3 input capture signal from corresponding multi-function pin
#1 : 1
Enable the channel 3 input capture signal from corresponding multi-function pin
End of enumeration elements list.
CH2RFORDER : None
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM_CFL2 is the first captured data to memory
#1 : 1
PWM_CRL2 is the first captured data to memory
End of enumeration elements list.
CH23CASK : Cascade channel 2 and channel 3 PWM counter for capturing usage
bits : 29 - 29 (1 bit)
access : read-write
CAPRELOADREN3 : Reload CNR3 When CH3 Rising Capture Event Comes\n
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising capture reload for CH3 Disabled
#1 : 1
Rising capture reload for CH3 Enabled
End of enumeration elements list.
CAPRELOADFEN3 : Reload CNR3 When CH3 Falling Capture Event Comes \n
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling capture reload for CH3 Disabled
#1 : 1
Falling capture reload for CH3 Enabled
End of enumeration elements list.
Capture Interrupt Enable Register
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRL_IE0 : Channel 0 Rising Latch Interrupt Enable ON/OFF\nWhen Enabled, if Capture detects Channel 0 has rising transition, Capture issues an Interrupt.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising latch interrupt Disabled
#1 : 1
Rising latch interrupt Enabled
End of enumeration elements list.
CFL_IE0 : Channel 0 Falling Latch Interrupt Enable ON/OFF\nWhen Enabled, if Capture detects Channel 0 has falling transition, Capture issues an Interrupt.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling latch interrupt Disabled
#1 : 1
Falling latch interrupt Enabled
End of enumeration elements list.
CRL_IE1 : Channel 1 Rising Latch Interrupt Enable Control\nWhen Enabled, if Capture detects Channel 1 has rising transition, Capture issues an Interrupt.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising latch interrupt Disabled
#1 : 1
Rising latch interrupt Enabled
End of enumeration elements list.
CFL_IE1 : Channel 1 Falling Latch Interrupt Enable Control\nWhen Enabled, if Capture detects Channel 1 has falling transition, Capture issues an Interrupt.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling latch interrupt Disabled
#1 : 1
Falling latch interrupt Enabled
End of enumeration elements list.
CRL_IE2 : Channel 2 Rising Latch Interrupt Enable ON/OFF\nWhen Enabled, if Capture detects Channel 2 has rising transition, Capture issues an Interrupt.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising latch interrupt Disabled
#1 : 1
Rising latch interrupt Enabled
End of enumeration elements list.
CFL_IE2 : Channel 2 Falling Latch Interrupt Enable ON/OFF\nWhen Enabled, if Capture detects Channel 2 has falling transition, Capture issues an Interrupt.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling latch interrupt Disabled
#1 : 1
Falling latch interrupt Enabled
End of enumeration elements list.
CRL_IE3 : Channel 3 Rising Latch Interrupt Enable ON/OFF\nWhen Enabled, if Capture detects Channel 3 has rising transition, Capture issues an Interrupt.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising latch interrupt Disabled
#1 : 1
Rising latch interrupt Enabled
End of enumeration elements list.
CFL_IE3 : Channel 3 Falling Latch Interrupt Enable ON/OFF\nWhen Enabled, if Capture detects Channel 3 has falling transition, Capture issues an Interrupt.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling latch interrupt Disabled
#1 : 1
Falling latch interrupt Enabled
End of enumeration elements list.
Capture Interrupt Indication Register
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPIF0 : Capture0 Interrupt Indication Flag
If channel 0 rising latch interrupt (CRL_IE0, PWM_CAPINTEN[0]) is enabled, a rising transition occurs at input channel 0 will result in CAPIF0 to high Similarly, a falling transition will cause CAPIF0 to be set high if channel 0 falling latch interrupt (CFL_IE0, PWM_CAPINTEN[1]) is enabled. This flag is cleared by software with a write 1 on it.
bits : 0 - 0 (1 bit)
access : read-write
CRLI0 : PWM_CRL0 Latched Indicator Bit\nWhen input channel 0 has a rising transition, PWM0_CRL0 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write
CFLI0 : PWM_CFL0 Latched Indicator Bit\nWhen input channel 0 has a falling transition, PWM0_CFL0 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
bits : 2 - 2 (1 bit)
access : read-write
CAPOVR0 : Capture Rising Flag Over Run for Channel 0\nThis flag indicate CRL0 update faster than software reading it when it is set \nThis bit will be cleared automatically when user clears CRLI0 (PWM_CAPINTSTS[1]).
bits : 3 - 3 (1 bit)
access : read-write
CAPOVF0 : Capture Falling Flag Over Run for Channel 0\nThis flag indicate CFL0 update faster than software read it when it is set\nThis bit will be cleared automatically when user clear CFLI0 (PWM_CAPINTSTS[2])
bits : 4 - 4 (1 bit)
access : read-write
CAPIF1 : Capture1 Interrupt Indication Flag
If channel 1 rising latch interrupt (CRL_IE1, PWM_CAPINTEN[8]) is enabled, a rising transition occurs at input channel 1 will result in CAPIF1 to high Similarly, a falling transition will cause CAPIF1 to be set high if channel 1 falling latch interrupt (CFL_IE1, PWM_CAPINTEN[9]) is enabled. This flag is cleared by software with a write 1 on it.
bits : 8 - 8 (1 bit)
access : read-write
CRLI1 : PWM_CRL1 Latched Indicator Bit\nWhen input channel 1 has a rising transition, PWM_CRL1 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
bits : 9 - 9 (1 bit)
access : read-write
CFLI1 : PWM_CFL1 Latched Indicator Bit\nWhen input channel 1 has a falling transition, PWM_CFL1 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
bits : 10 - 10 (1 bit)
access : read-write
CAPOVR1 : Capture Rising Flag Over Run for Channel 1\nThis flag indicate CRL1 update faster than software reading it when it is set \nThis bit will be cleared automatically when user clear CRLI1 (PWM_CAPINTSTS[9])
bits : 11 - 11 (1 bit)
access : read-write
CAPOVF1 : Capture Falling Flag Over Run for Channel 1\nThis flag indicate CFL1 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CFLI1 (PWM_CAPINTSTS[10])
bits : 12 - 12 (1 bit)
access : read-write
CAPIF2 : Capture2 Interrupt Indication Flag
If channel 2 rising latch interrupt (CRL_IE2, PWM_CAPINTEN[16]) is enabled, a rising transition occurs at input channel 2 will result in CAPIF2 to high Similarly, a falling transition will cause CAPIF2 to be set high if channel 2 falling latch interrupt (CFL_IE2, PWM_CAPINTEN[17]) is enabled. This flag is cleared by software with a write 1 on it.
bits : 16 - 16 (1 bit)
access : read-write
CRLI2 : PWM_CRL2 Latched Indicator Bit\nWhen input channel 2 has a rising transition, PWM0_CRL2 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
bits : 17 - 17 (1 bit)
access : read-write
CFLI2 : PWM_CFL2 Latched Indicator Bit\nWhen input channel 2 has a falling transition, PWM0_CFL2 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
bits : 18 - 18 (1 bit)
access : read-write
CAPOVR2 : Capture Rising Flag Over Run for Channel 2\nThis flag indicate CRL2 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CRLI2 (PWM_CAPINTSTS[17])
bits : 19 - 19 (1 bit)
access : read-write
CAPOVF2 : Capture Falling Flag Over Run for Channel 2 \nThis flag indicate CFL2 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CFLI2 (PWM_CAPINTSTS[18])
bits : 20 - 20 (1 bit)
access : read-write
CAPIF3 : Capture3 Interrupt Indication Flag
If channel 3 rising latch interrupt (CRL_IE3, PWM_CAPINTEN[24]) is enabled, a rising transition occurs at input channel 3 will result in CAPIF3 to high Similarly, a falling transition will cause CAPIF3 to be set high if channel 3 falling latch interrupt (CFL_IE3, PWM_CAPINTEN[25]) is enabled. This flag is cleared by software with a write 1 on it.
bits : 24 - 24 (1 bit)
access : read-write
CRLI3 : PWM_CRL3 Latched Indicator Bit\nWhen input channel 3 has a rising transition, PWM_CRL3 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
bits : 25 - 25 (1 bit)
access : read-write
CFLI3 : PWM_CFL3 Latched Indicator Bit\nWhen input channel 3 has a falling transition, PWM_CFL3 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
bits : 26 - 26 (1 bit)
access : read-write
CAPOVR3 : Capture Rising Flag Over Run for Channel 3\nThis flag indicate CRL3update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CRLI3 (PWM_CAPINTSTS[25])
bits : 27 - 27 (1 bit)
access : read-write
CAPOVF3 : Capture Falling Flag Over Run for Channel 3 \nThis flag indicate CFL3 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CFLI3 (PWM_CAPINTSTS[26])
bits : 28 - 28 (1 bit)
access : read-write
Capture Rising Latch Register (Channel 0)
address_offset : 0x60 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CRL : Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition.
bits : 0 - 15 (16 bit)
access : read-only
CRL_H : Upper Half Word of 32-bit Capture Data When Cascade Enable Control\nWhen cascade is enabled for capture channel 0, 2,the original 16 bit counter extend to 32 bit, and capture result CRL0 and CRL2 are also extend to 32 bit,
bits : 16 - 31 (16 bit)
access : read-only
Capture Falling Latch Register (Channel 0)
address_offset : 0x64 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CFL : Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has Falling transition.
bits : 0 - 15 (16 bit)
access : read-only
CFL_H : Upper Half Word of 32-bit Capture Data When Cascade Enable Control\nWhen cascade is enabled for capture channel 0, 2, the original 16 bit counter will be extended to 32 bit, and capture result CFL0 and CFL2 are also extended to 32 bit,
bits : 16 - 31 (16 bit)
access : read-only
Capture Rising Latch Register (Channel 1)
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Capture Falling Latch Register (Channel 1)
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Capture Rising Latch Register (Channel 2)
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Capture Falling Latch Register (Channel 2)
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Capture Rising Latch Register (Channel 3)
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Capture Falling Latch Register (Channel 3)
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Control Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0EN : PWM-timer 0 Enable/Disable Start Run\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM-Timer 0 Running Stopped
#1 : 1
PWM-Timer 0 Start Run Enabled
End of enumeration elements list.
CH0INV : PWM-timer 0 Output Inverter ON/OFF\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverter OFF
#1 : 1
Inverter ON
End of enumeration elements list.
CH0MOD : PWM-timer 0 Continuous/One-shot Mode\nNote: If there is a rising transition at this bit, it will cause CN and CM of PWM0_DUTY0 to be cleared.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
One-Shot Mode
#1 : 1
Continuous Mode
End of enumeration elements list.
DZEN01 : Dead-zone 0 Generator Enable/Disable Control\nNote: When Dead-Zone Generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
DZEN23 : Dead-zone 2 Generator Enable/Disable Control\nNote: When Dead-Zone Generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CH1EN : PWM-timer 1 Enable/Disable Start Run\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM-Timer 1 Running Stopped
#1 : 1
PWM-Timer 1 Start Run Enabled
End of enumeration elements list.
CH1INV : PWM-timer 1 Output Inverter ON/OFF\n
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverter OFF
#1 : 1
Inverter ON
End of enumeration elements list.
CH1MOD : PWM-timer 1 Continuous/One-shot Mode\nNote: If there is a rising transition at this bit, it will cause CN and CM of PWM0_DUTY1 to be cleared.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
One-Shot Mode
#1 : 1
Continuous Mode
End of enumeration elements list.
CH2EN : PWM-timer 2 Enable/Disable Start Run\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM-Timer 2 Running Stopped
#1 : 1
PWM-Timer 2 Start Run Enabled
End of enumeration elements list.
CH2INV : PWM-timer 2 Output Inverter ON/OFF\n
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverter OFF
#1 : 1
Inverter ON
End of enumeration elements list.
CH2MOD : PWM-timer 2 Continuous/One-shot Mode\nNote: If there is a rising transition at this bit, it will cause CN and CM of PWM0_DUTY2 be cleared.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
One-Shot Mode
#1 : 1
Continuous Mode
End of enumeration elements list.
CH3EN : PWM-timer 3 Enable/Disable Start Run\n
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM-Timer 3 Running Stopped
#1 : 1
PWM-Timer 3 Start Run Enabled
End of enumeration elements list.
CH3INV : PWM-timer 3 Output Inverter ON/OFF\n
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverter OFF
#1 : 1
Inverter ON
End of enumeration elements list.
CH3MOD : PWM-timer 3 Continuous/One-shot Mode\nNote: If there is a rising transition at this bit, it will cause CN and CM of PWM0_DUTY3 to be cleared.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
One-Shot Mode
#1 : 1
Continuous Mode
End of enumeration elements list.
PWMTYPE01 : Channel 0,1 Counter Mode\n
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge-aligned Mode
#1 : 1
Center-aligned Mode
End of enumeration elements list.
PWMTYPE23 : Channel 2,3 Counter Mode\n
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge-aligned Mode
#1 : 1
Center-aligned Mode
End of enumeration elements list.
PDMA Channel 0 Captured Data
address_offset : 0x80 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PDMACH01 : Captured Data of Channel 0\nWhen CH01CASK is disabled, this byte is 0\nWhen CH01CASK is enabled, It is the 1st byte of 32 bit capturing data for channel 0.\nNote: This register is used as a buffer to transfer PWM captured rising or falling data to memory by PDMA.
bits : 0 - 7 (8 bit)
access : read-only
PDMACH02 : Captured Data of Channel 0\nWhen CH01CASK is disabled, this byte is 0\nWhen CH01CASK is enabled, It is the 2nd byte of 32 bit capturing data for channel 0.\nNote: This register is used as a buffer to transfer PWM captured rising or falling data to memory by PDMA.
bits : 8 - 15 (8 bit)
access : read-only
PDMACH03 : Captured Data of Channel 0\nWhen CH01CASK is disabled, this byte is 0\nWhen CH01CASK is enabled, It is the 3rd byte of 32 bit capturing data for channel 0.\nNote: This register is used as a buffer to transfer PWM captured rising or falling data to memory by PDMA.
bits : 16 - 23 (8 bit)
access : read-only
PDMACH04 : Captured Data of Channel 0\nWhen CH01CASK is disabled, this byte is 0\nWhen CH01CASK is enabled, It is the 4th byte of 32 bit capturing data for channel 0.\nNote: This register is used as a buffer to transfer PWM captured rising or falling data to memory by PDMA.
bits : 24 - 31 (8 bit)
access : read-only
PDMA Channel 2 Captured Data
address_offset : 0x84 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PDMACH21 : Captured Data of Channel 2\nWhen CH23CASK is disabled, this byte is 0\nWhen CH23CASK is enabled, It is the 1st byte of 32 bit capturing data for channel 0.\nNote: This register is used as a buffer to transfer PWM captured rising or falling data to memory by PDMA.
bits : 0 - 7 (8 bit)
access : read-only
PDMACH22 : Captured Data of Channel 2\nWhen CH23CASK is disabled, this byte is 0\nWhen CH23CASK is enabled, It is the 2nd byte of 32 bit capturing data for channel 0.\nNote: This register is used as a buffer to transfer PWM captured rising or falling data to memory by PDMA.
bits : 8 - 15 (8 bit)
access : read-only
PDMACH23 : Captured Data of Channel 2\nWhen CH23CASK is disabled, this byte is 0\nWhen CH23CASK is enabled, It is the 3rd byte of 32 bit capturing data for channel 0.\nNote: This register is used as a buffer to transfer PWM captured rising or falling data to memory by PDMA.
bits : 16 - 23 (8 bit)
access : read-only
PDMACH24 : Captured Data of Channel 2\nWhen CH23CASK is disabled, this byte is 0\nWhen CH23CASK is enabled, It is the 4th byte of 32 bit capturing data for channel 0.\nNote: This register is used as a buffer to transfer PWM captured rising or falling data to memory by PDMA.
bits : 24 - 31 (8 bit)
access : read-only
PWM Center-triggered Control Register
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRGCH0EN : PWM CH0 Center-triggered Enable Control\nNote: The center-triggered function is only valid in PWM center-aligned mode.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM CH0 center-triggered function Disabled
#1 : 1
PWM CH0 center-triggered function Enabled
End of enumeration elements list.
TRGCH1EN : PWM CH1 Center-triggered Enable Control\nNote: The center-triggered function is only valid in PWM center-aligned mode.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM CH1 center-triggered function Disabled
#1 : 1
PWM CH1 center-triggered function Enabled
End of enumeration elements list.
TRGCH2EN : PWM CH2 Center-triggered Enable Control\nNote: The center-triggered function is only valid in PWM center-aligned mode.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM CH2 center-triggered function Disabled
#1 : 1
PWM CH2 center-triggered function Enabled
End of enumeration elements list.
TRGCH3EN : PWM CH3 Center-triggered Enable Control\nNote: The center-triggered function is only valid in PWM center-aligned mode.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM CH3 center-triggered function Disabled
#1 : 1
PWM CH3 center-triggered function Enabled
End of enumeration elements list.
PWM Center-triggered Indication Register
address_offset : 0x8C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADTRG0Flag : PWM CH0 Center-triggered Flag\nNote: This flag is only valid in center-aligned mode, and software could write 1 into this bit to clear the flag
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
PWM CH0 has not crossed half of PWM period yet
#1 : 1
PWM CH0 has crossed half of PWM period
End of enumeration elements list.
ADTRG1Flag : PWM CH1 Center-triggered Flag\nNote: This flag is only valid in center-aligned mode, and software could write 1 into this bit to clear the flag
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
PWM CH1 has not crossed half of PWM period yet
#1 : 1
PWM CH1 has crossed half of PWM period
End of enumeration elements list.
ADTRG2Flag : PWM CH2 Center-triggered Flag\nNote: This flag is only valid in center-aligned mode, and software could write 1 into this bit to clear the flag
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
PWM CH2 has not crossed half of PWM period yet
#1 : 1
PWM CH2 has crossed half of PWM period
End of enumeration elements list.
ADTRG3Flag : PWM CH3 Center-triggered Flag\nNote: This flag is only valid in center-aligned mode, and software could write 1 into this bit to clear the flag
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
PWM CH3 has not crossed half of PWM period yet
#1 : 1
PWM CH3 has crossed half of PWM period
End of enumeration elements list.
PWM Interrupt Enable Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMIE0 : PWM Timer 0 Interrupt Enable Control\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
TMIE1 : PWM Timer 1 Interrupt Enable Control\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
TMIE2 : PWM Timer 2 Interrupt Enable Control\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
TMIE3 : PWM Timer 3 Interrupt Enable Control\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
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