WWDTRLD

WWDTVAL

WWDTCR

WWDT_IER (IER)

WWDTSTS

WWDTRLD : Window Watchdog Timer Reload Counter Register\nWriting 0x00005AA5 to this register will reload the Window Watchdog Timer counter value to 0x3F. \nNote: This register can only be written when WWDT counter value between 0 and WINCMP, otherwise WWDT will generate RESET signal.
bits : 0 - 31 (32 bit)
access : write-only

WWDTVAL : WWDT Counter Value\nThis register reflects the current counter value of window watchdog.
bits : 0 - 5 (6 bit)
access : read-only

WWDTEN : Window Watchdog Enable Control\nSet this bit to enable Window Watchdog timer.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PERIODSEL : WWDT Pre-scale Period Select\nThese three bits select the pre-scale for the WWDT counter period.\nPlease refer to Table 6 14.
bits : 8 - 11 (4 bit)
access : read-write

WINCMP : WWDT Window Compare Register\nSet this register to adjust the valid reload window. \nNote: WWDTRLD register can only be written when WWDT counter value between 0 and WINCMP, otherwise WWDT will generate RESET signal.
bits : 16 - 21 (6 bit)
access : read-write

DBGEN : WWDT Debug Enable Control\n
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WWDTIE : WWDT Interrupt Enable Control\nSetting this bit will enable the Window Watchdog timer interrupt function.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WWDTIF : WWDT Compare Match Interrupt Flag\nWhen WWCMP match the WWDT counter, then this bit is set to 1. This bit can be cleared by writing one to it.
bits : 0 - 0 (1 bit)
access : read-write

WWDTRF : WWDT Reset Flag\nWhen WWDT counter down count to 0 or write WWDTRLD during WWDT counter larger than WINCMP, chip will be reset and this bit is set to 1. This bit can be cleared by writing one to it.
bits : 1 - 1 (1 bit)
access : read-write