\n
address_offset : 0x0 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x30 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
UART Receive Buffer Register.
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RBR : Receive Buffer Register\nBy reading this register, the UART will return an 8-bit data received from RX pin (LSB first).
bits : 0 - 7 (8 bit)
access : read-only
UART Transmit Holding Register.
address_offset : 0x0 Bytes (0x0)
access : write-only
reset_value : 0x0
alternate_register : UART_RBR
reset_Mask : 0x0
THR : Transmit Holding Register\nBy writing to this register, the UART will send out an 8-bit data through the TX pin (LSB first).
bits : 0 - 7 (8 bit)
access : write-only
UART Interrupt Status Register.
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDA_IS : Receive Data Available Interrupt Flag (Read Only)
When the number of bytes in the RX-FIFO equals the RFITL then the RDA_IF will be set. If RDA_IEN (UART_IER[0]) is set then the RDA interrupt will be generated.
Note: This bit is read only and it will be cleared when the number of unread bytes of RX-FIFO drops below the threshold level (RFITL).
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
No Receive Data available interrupt is generated
#1 : 1
Receive Data available interrupt is generated
End of enumeration elements list.
THRE_IS : Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX-FIFO is transferred to Transmitter Shift Register. If THRE_IEN (UART_IER[1]) is set that the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into THR (TX-FIFO not empty).
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
No Transmit Holding register empty interrupt is generated
#1 : 1
Transmit Holding register empty interrupt generated
End of enumeration elements list.
RLS_IS : Receive Line Interrupt Status Flag (Read Only)
This bit is set when the RX received data has parity error (PE_F (UART_FSR[4])), framing error (FE_F (UART_FSR[5])), break error (BI_F (UART_FSR[6])) or RS-485 detect address byte (RS-485_ADDET_F (UART_TRSR[0])).If RLS_IE (UART_IER[2]) is set then the RLS interrupt will be generated.
Note1: This bit is read only, but can be cleared by it by writing 1 to BI_F (UART_FSR[6]), FE_F (UART_FSR[5]), PE_F (UART_FSR[4]) or RS-485_ADDET_F (UART_TRSR[0]).
Note2: This bit is cleared when the BI_F, FE_F, PE_F and RS-485_ADDET_F are cleared.
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
No Receive Line interrupt is generated
#1 : 1
Receive Line interrupt is generated
End of enumeration elements list.
MODEM_IS : MODEM Interrupt Status Flag (Read Only)
Note: This bit is read only, but can be cleared by it by writing 1 to DCT_F (UART_MCSR[18]).
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
No MODEM interrupt is generated
#1 : 1
MODEM interrupt is generated
End of enumeration elements list.
RTO_IS : RX Time-out Interrupt Status Flag (Read Only)\nThis bit is set when the RX-FIFO is not empty and no activities occur in the RX-FIFO and the time-out counter equal to TOIC. If RTO_IE (UART_IER[4]) is set then the tout interrupt will be generated. \nNote: This bit is read only and user can read UART_RBR (RX is in active) to clear it.
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
No RX Time-Out interrupt is generated
#1 : 1
RX Time-Out interrupt is generated
End of enumeration elements list.
BUF_ERR_IS : Buffer Error Interrupt Status Flag (Read Only)
This bit is set when the TX or RX-FIFO overflowed. When BUF_ERR_IS is set, the transfer maybe not correct. If BUF_ERR_IE (UART_IER[5]) is set then the buffer error interrupt will be generated.
Note1: This bit is read only, but can be cleared by it by writing 1 to TX_OVER_F (UART_FSR[8]) or RX_OVER_F (UART_FSR[0]).
Note2: This bit is cleared when both the TX_OVER_F and RX_OVER_F are cleared.
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
No Buffer error interrupt is generated
#1 : 1
Buffer error interrupt is generated
End of enumeration elements list.
WAKE_IS : Wake-up Interrupt Status Flag (Read Only)
This bit is set in Power-down mode, the receiver received data or CTSn signal. If WAKE_IE (UART_IER[6]) is set then the wake-up interrupt will be generated.
Note: This bit is read only, but can be cleared by it by writing 1 to it.
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
No Wake-Up interrupt is generated
#1 : 1
Wake-Up interrupt is generated
End of enumeration elements list.
ABAUD_IS : Auto-baud Rate Interrupt Status Flag (Read Only)
This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABAUD_IE (UART_IER[7]) is set then the auto-baud rate interrupt will be generated.
Note1: This bit is read only, but can be cleared by it by writing 1 to ABAUD_TOUT_F (UART_TRSR[2]) or ABAUD_F (UART_TRSR[1]).
Note2: This bit is cleared when both the ABAUD_TOUT_F and ABAUD_F are cleared.
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
No Auto-Baud Rate interrupt is generated
#1 : 1
Auto-Baud Rate interrupt is generated
End of enumeration elements list.
LIN_IS : LIN Interrupt Status Flag (Read Only)
This bit is set when the LIN TX header transmitted, RX header received or the SIN does not equal SOUT and if LIN_IE(UART_IER[8]) is set then the LIN interrupt will be generated.
Note1: This bit is read only, but can be cleared by it by writing 1 to BIT_ERR_F (UART_TRSR[5]), LIN_TX_F (UART_TRSR[3]) or LIN_RX_F (UART_TRSR[4]).
Note2: This bit is cleared when both the BIT_ERR_F, LIN_TX_F and LIN_RX_F are cleared.
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
No LIN interrupt is generated
#1 : 1
LIN interrupt is generated
End of enumeration elements list.
UART Transfer State Status Register.
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RS_485_ADDET_F : RS-485 Address Byte Detection Status Flag (Read Only)
Note1: This field is used for RS-485 mode.
Note2: This bit is read only, but can be cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
No RS-485 address detection interrupt is generated
#1 : 1
RS-485 address detection interrupt is generated
End of enumeration elements list.
ABAUD_F : Auto-baud Rate Interrupt (Read Only)
This bit is set to logic 1 when auto-baud rate detect function finished.
Note: This bit is read only, but can be cleared by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
No Auto- Baud Rate interrupt is generated
#1 : 1
Auto-Baud Rate interrupt is generated
End of enumeration elements list.
ABAUD_TOUT_F : Auto-baud Rate Time-out Interrupt (Read Only)
This bit is set to logic 1 in Auto-baud Rate Detect mode and the baud rate counter is overflow.
Note: This bit is read only, but can be cleared by writing 1 to it.
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
No Auto-Baud Rate Time-Out interrupt is generated
#1 : 1
Auto-Baud Rate Time-Out interrupt is generated
End of enumeration elements list.
LIN_TX_F : LIN TX Interrupt Flag (Read Only)
This bit is set to logic 1 when LIN transmitted header field. The header may be break field or break field + sync field or break field + sync field + PID field , it can be choose by setting LIN_HEAD_SEL (UART_ALT_CTL[5:4]) register.
Note: This bit is read only, but can be cleared by writing 1 to it.
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
No LIN Tx interrupt is generated
#1 : 1
LIN Tx interrupt is generated
End of enumeration elements list.
LIN_RX_F : LIN RX Interrupt Flag (Read Only)
This bit is set to logic 1 when received LIN header field. The header may be break field or break field + sync field or break field + sync field + PID field , and it can be choose by setting LIN_HEAD_SEL (UART_ALT_CTL[5:4]) register.
Note: This bit is read only, but can be cleared by writing 1 to it.
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
No LIN Rx interrupt is generated
#1 : 1
LIN Rx interrupt is generated
End of enumeration elements list.
BIT_ERR_F : Bit Error Detect Status Flag (Read Only)\nAt TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state is not equal to the output pin (SOUT) state, BIT_ERR_F will be set.\nWhen occur bit error, hardware will generate an interrupt to CPU (INT_LIN).\n
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
No Bit error interrupt is generated
#1 : 1
Bit error interrupt is generated
End of enumeration elements list.
LIN_RX_SYNC_ERR_F : LIN RX SYNC Error Flag (Read Only)
This bit is set to logic 1 when LIN received incorrect SYNC field.
User can choose the header by setting LIN_HEAD_SEL (UART_ALT_CTL[5:4]) register.
Note: This bit is read only, but can be cleared by writing 1 to LIN_RX_F.
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
No LIN Rx sync error is generated
#1 : 1
LIN Rx sync error is generated
End of enumeration elements list.
UART FIFO State Status Register.
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_OVER_F : RX Overflow Error Status Flag (Read Only)
This bit is set when RX-FIFO overflow.
If the number of bytes of received data is greater than RX-FIFO (UART_RBR) size, 16 bytes of UART0/UART1, this bit will be set.
Note: This bit is read only, but it can be cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
RX FIFO is not overflow
#1 : 1
RX FIFO is overflow
End of enumeration elements list.
RX_EMPTY_F : Receiver FIFO Empty (Read Only)\nThis bit initiate RX-FIFO empty or not.\nWhen the last byte of RX-FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.\n
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
RX FIFO is not empty
#1 : 1
RX FIFO is empty
End of enumeration elements list.
RX_FULL_F : Receiver FIFO Full (Read Only)\nThis bit initiates RX-FIFO full or not.\nThis bit is set when RX_POINTER_F is equal to 16, otherwise is cleared by hardware.\n
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
RX FIFO is not full
#1 : 1
RX FIFO is full
End of enumeration elements list.
PE_F : Parity Error State Status Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid parity bit , and it is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but it can be cleared by writing 1 to it.
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
No parity error is generated
#1 : 1
Parity error is generated
End of enumeration elements list.
FE_F : Framing Error Status Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as a logic 0 ), and it is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but it can be cleared by writing 1 to it.
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
No framing error is generated
#1 : 1
Framing error is generated
End of enumeration elements list.
BI_F : Break Status Flag (Read Only)
This bit is set to a logic 1 whenever the received data input(RX) is held in the spacing state (logic 0 ) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits) and it is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but it can be cleared by writing 1 to it.
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
No Break interrupt is generated
#1 : 1
Break interrupt is generated
End of enumeration elements list.
TX_OVER_F : TX Overflow Error Interrupt Status Flag (Read Only)
If TX-FIFO (UART_THR) is full, an additional write to UART_THR will cause this bit to logic 1 .
Note: This bit is read only, but it can be cleared by writing 1 to it.
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
TX FIFO is not overflow
#1 : 1
TX FIFO is overflow
End of enumeration elements list.
TX_EMPTY_F : Transmitter FIFO Empty (Read Only)
This bit indicates TX-FIFO empty or not.
When the last byte of TX-FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX-FIFO not empty).
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
TX FIFO is not empty
#1 : 1
TX FIFO is empty
End of enumeration elements list.
TX_FULL_F : Transmitter FIFO Full (Read Only)
This bit indicates TX-FIFO full or not.
This bit is set when TX_POINTER_F is equal to 16, otherwise is cleared by hardware.
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
#0 : 0
TX FIFO is not full
#1 : 1
TX FIFO is full
End of enumeration elements list.
TE_F : Transmitter Empty Status Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted. \nThis bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.\n
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
#0 : 0
TX FIFO is not empty
#1 : 1
TX FIFO is empty
End of enumeration elements list.
RX_POINTER_F : RX-fIFO Pointer (Read Only)\nThis field indicates the RX-FIFO Buffer Pointer. When UART receives one byte from external device, RX_POINTER_F increases one. When one byte of RX-FIFO is read by CPU, RX_POINTER_F decreases one.
bits : 16 - 20 (5 bit)
access : read-only
TX_POINTER_F : TX-fIFO Pointer (Read Only)\nThis field indicates the TX-FIFO Buffer Pointer. When CPU writes one byte data into UART_THR, TX_POINTER_F increases one. When one byte of TX-FIFO is transferred to Transmitter Shift Register, TX_POINTER_F decreases one.
bits : 24 - 28 (5 bit)
access : read-only
UART Modem State Status Register.
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEV_RTS : RTSn Trigger Level \n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
low level triggered
#1 : 1
high level triggered
End of enumeration elements list.
RTS_ST : RTSn Pin State (Read Only)\nThis bit is the pin status of RTSn.\n
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
RTS pin input is low level voltage logic state
#1 : 1
RTS pin input is high level voltage logic state
End of enumeration elements list.
LEV_CTS : CTSn Trigger Level\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low level triggered
#1 : 1
High level triggered
End of enumeration elements list.
CTS_ST : CTSn Pin Status (Read Only)\nThis bit is the pin status of CTSn. \n
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
CTS pin input is low level voltage logic state
#1 : 1
CTS pin input is high level voltage logic state
End of enumeration elements list.
DCT_F : Detect CTSn State Change Status Flag (Read Only)
This bit is set whenever CTSn input has change state, and it will generate Modem interrupt to CPU when MODEM_IE (UART_IER[3]).
Note: This bit is read only, but it can be cleared by writing 1 to it.
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
#0 : 0
CTS input has not change state
#1 : 1
CTS input has change state
End of enumeration elements list.
UART Time-out Control State Register.
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOIC : Time-out Comparator
The time-out counter resets and starts counting whenever the RX-FIFO receives a new data word.
Note1: Fill all 0 to this field indicates to disable this function.
Note2: The real time-out value is TOIC + 1.
Note3: The counting clock is baud rate clock.
Note4: The UART data format is start bit + 8 data bits + parity bit + stop bit, although software can configure this field by any value but it is recommend to filled this field great than 0xA.
bits : 0 - 8 (9 bit)
access : read-write
DLY : TX Delay Time Value
This field is used to programming the transfer delay time between the last stop bit and next start bit.
Note1: Fill all 0 to this field indicates to disable this function.
Note2: The real delay value is DLY.
Note3: The counting clock is baud rate clock.
bits : 16 - 23 (8 bit)
access : read-write
UART Baud Rate Divisor Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRD : Baud Rate Divider \n
bits : 0 - 15 (16 bit)
access : read-write
DIV_16_EN : Divider 16 Enable Control
Note: In IrDA mode, this bit must clear to 0 .
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The equation of baud rate is UART_CLK / [ (BRD+1)]
#1 : 1
The equation of baud rate is UART_CLK / [16 * (BRD+1)]
End of enumeration elements list.
UART IrDA Control Register.
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_SELECT : TX_SELECT\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Select IrDA receiver
#1 : 1
Select IrDA transmitter
End of enumeration elements list.
INV_TX : INV_TX\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
TX output signal no inversion
#1 : 1
TX output signal inversion
End of enumeration elements list.
INV_RX : INV_RX\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
RX input signal no inversion
#1 : 1
RX input signal inversion
End of enumeration elements list.
UART Alternate Control State Register.
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LIN_TX_BCNT : LIN TX Break Field Count \nThe field contains 3-bit LIN TX break field count.\nNote: The break field length is LIN_TX_BCNT + 8.
bits : 0 - 2 (3 bit)
access : read-write
LIN_HEAD_SEL : LIN Header Selection\n
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
The LIN header includes break field
#01 : 1
The LIN header includes break field + sync field
#10 : 2
The LIN header includes break field + sync field + PID field
#11 : 3
Reserved
End of enumeration elements list.
LIN_RX_EN : LIN RX Enable Control\nWhen LIN RX mode enabled and received a break field or sync field or PID field (Select by LIN_Header_SEL), the controller will generator a interrupt to CPU (INT_LIN)\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
LIN RX mode Disabled
#1 : 1
LIN RX mode Enabled
End of enumeration elements list.
LIN_TX_EN : LIN TX Header Trigger Enable Control\nNote1: This bit will be cleared automatically and generate a interrupt to CPU (INT_LIN).\nNote2: If user wants to receive transmit data, it recommended to enable LIN_RX_EN bit.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
LIN TX Header Trigger Disabled
#1 : 1
LIN TX Header Trigger Enabled
End of enumeration elements list.
BIT_ERR_EN : Bit Error Detect Enable Control\nNote: In LIN function mode, when bit error occurs, hardware will generate an interrupt to CPU (INT_LIN).
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bit error detection Disabled
#1 : 1
Bit error detection Enabled
End of enumeration elements list.
RS_485_NMM : RS-485 Normal Multi-drop Operation Mode (NMM Mode)\nNote: It can't be active in RS-485_AAD Operation mode.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
RS-485 Normal Multi-drop Operation mode (NMM) Disabled
#1 : 1
RS-485 Normal Multi-drop Operation mode (NMM) Enabled
End of enumeration elements list.
RS_485_AAD : RS-485 Auto Address Detection Operation Mode (AAD Mode)\nNote: It can't be active in RS-485_NMM Operation mode.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
RS-485 Auto Address Detection Operation mode (AAD) Disabled
#1 : 1
RS-485 Auto Address Detection Operation mode (AAD) Enabled
End of enumeration elements list.
RS_485_AUD : RS-485 Auto Direction Mode (AUD Mode)\nNote: It can be active in RS-485_AAD or RS-485_NMM operation mode.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
RS-485 Auto Direction mode (AUD) Disabled
#1 : 1
RS-485 Auto Direction mode (AUD) Enabled
End of enumeration elements list.
RS_485_ADD_EN : RS-485 Address Detection Enable Control\nThis bit is used to enable RS-485 hardware address detection mode.\nNote: This field is used for RS-485 any operation mode.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Address detection mode Disabled
#1 : 1
Address detection mode Enabled
End of enumeration elements list.
ADDR_PID_MATCH : Address / PID Match Value Register\nWhen in the RS-485 Function Mode, this field contains the RS-485 address match values.\nWhen in the LIN Function mode, this field contains the LIN protected identifier field, software fills ID0~ID5 (ADDR_PID_MATCH [5:0]), hardware will calculate P0 and P1.\n\nNote: This field is used for RS-485 auto address detection mode or used for LIN protected identifier field (PID).
bits : 24 - 31 (8 bit)
access : read-write
UART Function Select Register.
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FUN_SEL : Function Select Enable Control\n
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
UART function mode
#01 : 1
LIN function mode
#10 : 2
IrDA function mode
#11 : 3
RS-485 function mode
End of enumeration elements list.
UART Baud Rate Compensation
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BR_COMP : Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not. BR_COMP[7:0] is used to define the compensation of D[7:0] and BR_COM{[8] is used to define the parity bit.
bits : 0 - 8 (9 bit)
access : read-write
BR_COMP_DEC : Baud Rate Compensation Decrease\n
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Positive (increase one module clock) compensation for each compensated bit
#1 : 1
Negative (decrease one module clock) compensation for each compensated bit
End of enumeration elements list.
UART Control State Register.
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_RST : RX Software Reset\nWhen RX_RST is set, all the bytes in the receiving FIFO and RX internal state machine are cleared.\nNote: This bit will be auto cleared and take at least 3 UART engine clock cycles.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset the RX internal state machine and pointers
End of enumeration elements list.
TX_RST : TX Software Reset\nWhen TX_RST is set, all the bytes in the transmitting FIFO and TX internal state machine are cleared.\nNote: This bit will be auto cleared and take at least 3 UART engine clock cycles.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset the TX internal state machine and pointers
End of enumeration elements list.
RX_DIS : Receiver Disable Control
Note1: In RS-485 NMM mode, user can set this bit to receive data before detecting address byte.
Note2: In RS-485 AAD mode, this bit will be setting to 1 automatically.
Note3: In RS-485 AUD mode and LIN break + sync +PID header mode, hardware will control data automatically, so don't fill any value to this bit.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receiver Enabled
#1 : 1
Receiver Disabled
End of enumeration elements list.
TX_DIS : Transfer Disable Control\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transfer Enabled
#1 : 1
Transfer Disabled
End of enumeration elements list.
AUTO_RTS_EN : RTSn Auto-flow Control Enable Control\nWhen RTSn auto-flow is enabled, if the number of bytes in the RX-FIFO equals the RTS_TRI_LEV (UART_TLCTL[13:12]), the UART will reassert RTSn signal.\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
RTSn auto-flow control. Disabled
#1 : 1
RTSn auto-flow control Enabled
End of enumeration elements list.
AUTO_CTS_EN : CTSn Auto-flow Control Enable Control\nWhen CTSn auto-flow is enabled, the UART will send data to external device when CTSn input assert (UART will not send data to device until CTSn is asserted).\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
CTSn auto-flow control Disabled
#1 : 1
CTSn auto-flow control Enabled
End of enumeration elements list.
DMA_RX_EN : RX DMA Enable Control\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
RX PDMA service function Disabled
#1 : 1
RX PDMA service function Enabled
End of enumeration elements list.
DMA_TX_EN : TX DMA Enable Control\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
TX PDMA service function Disabled
#1 : 1
TX PDMA service function Enabled
End of enumeration elements list.
WAKE_CTS_EN : CTSn Wake-up Function Enable Control\nWhen the system is in Power-down mode, an external CTSn change will wake-up system from Power-down mode.\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
CTSn wake-up function Disabled
#1 : 1
CTSn wake-up function Enabled
End of enumeration elements list.
WAKE_DATA_EN : Incoming Data Wake-up Function Enable Control
Note: Hardware will clear this bit when the incoming data wake-up operation finishes and system clock work stable.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Incoming data wake-up function Disabled
#1 : 1
Incoming data wake-up function Enabled when the system is in Power-down mode, incoming data will wake-up system from Power-down mode
End of enumeration elements list.
ABAUD_EN : Auto-baud Rate Detect Enable Control\nNote: When the auto-baud rate detect operation finishes, hardware will clear this bit and the associated interrupt (INT_ABAUD) will be generated (If ABAUD_IE (UART_IER [7]) be enabled).
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Auto-baud rate detect function Disabled
#1 : 1
Auto-baud rate detect function Enabled
End of enumeration elements list.
WAKE_THRESH_EN : FIFO Threshold Reach Wake-up Function Enable Control\n
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Received FIFO threshold reach wake-up function Disabled
#1 : 1
Received FIFO threshold reach wake-up function Enabled when the system is in Power-down mode
End of enumeration elements list.
WAKE_RS485_AAD_EN : RS-485 Address Match Wake-up Function Enable Control\n
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
RS-485 ADD mode address match wake-up function Disabled
#1 : 1
RS-485 AAD mode address match wake-up function Enabled when the system is in Power-down mode
End of enumeration elements list.
PWM_SEL : PWM Channel Select for Modulation\nSelect the PWM channel to modulate with the UART transmit bus.\nThe others, no modulation of UART with PWM
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#000 : 0
PWM channel 0 modulate with UART TX
#001 : 1
PWM channel 1 modulate with UART TX
#010 : 2
PWM channel 2 modulate with UART TX
#011 : 3
PWM channel 3 modulate with UART TX
End of enumeration elements list.
UART Transfer Line Control Register.
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_LEN : Data Length\n
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Word length is 5-bit
#01 : 1
Word length is 6-bit
#10 : 2
Word length is 7-bit
#11 : 3
Word length is 8-bit
End of enumeration elements list.
NSB : Number of STOP Bit Length\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
1 STOP bit is generated in the transmitted data
#1 : 1
1.5 STOP bit is generated in the transmitted data when 5-bit word length is selected, and 2 STOP bit is generated when 6, 7 and 8 bits data length is selected
End of enumeration elements list.
PBE : Parity Bit Enable Control\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Parity bit is not generated (transmitting data) or checked (receiving data) during transfer
#1 : 1
Parity bit is generated or checked bet een the last data word it and stop bit of the serial data
End of enumeration elements list.
EPE : Even Parity Enable Control\nNote: This bit has effect only when PBE bit (parity bit enable) is set.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode
#1 : 1
Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode
End of enumeration elements list.
SPE : Stick Parity Enable Control
Note1: When bits PBE, EPE and SPE are set, the parity bit is transmitted and checked as 0 . When PBE and SPE are set and EPE is cleared, the parity bit is transmitted and checked as 1 .
Note2: In RS-485 mode, PBE, EPE and SPE can control bit 9, the bit 9 setting are shown as follows.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Stick parity Disabled
#1 : 1
Stick parity Enabled
End of enumeration elements list.
BCB : Break Control Bit
When this bit is set to logic 1 , the serial data output (TX) is forced to the Spacing State (logic 0 ). This bit acts only on TX pin and has no effect on the transmitter logic.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Break control Disabled
#1 : 1
Break control Enabled
End of enumeration elements list.
RFITL : RX-fIFO Interrupt (INT_RDA) Trigger Level
When the number of bytes in the receiving FIFO is equal to the RFITL then the RDA_IF will be set (if RDA_IE(IER[0]) is enabled, an interrupt will be generated)
Note: When operating in IrDA mode or RS-485 mode, the RFITL must be set to 0 .
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
RX FIFO Interrupt Trigger Level is 1 byte
#01 : 1
RX FIFO Interrupt Trigger Level is 4 bytes
#10 : 2
RX FIFO Interrupt Trigger Level is 8 bytes
#11 : 3
RX FIFO Interrupt Trigger Level is 14 bytes
End of enumeration elements list.
RTS_TRI_LEV : RTSn Trigger Level (For Auto-flow Control Use)\nNote: This field is used for auto RTSn flow control.
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 0
RTS Trigger Level is 1 byte
#01 : 1
RTS Trigger Level is 4 bytes
#10 : 2
RTS Trigger Level is 8 bytes
#11 : 3
RTS Trigger Level is 14 bytes
End of enumeration elements list.
UART Interrupt Enable Register.
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDA_IE : Receive Data Available Interrupt Enable Control\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
INT_RDA Disable
#1 : 1
INT_RDA Enabled
End of enumeration elements list.
THRE_IE : Transmit Holding Register Empty Interrupt Enable Control\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
INT_THRE Disable
#1 : 1
INT_THRE Enabled
End of enumeration elements list.
RLS_IE : Receive Line Status Interrupt Enable Control\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
INT_RLS Disable
#1 : 1
INT_RLS Enabled
End of enumeration elements list.
MODEM_IE : Modem Status Interrupt Enable Control\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
INT_MOS Disable
#1 : 1
INT_MOS Enabled
End of enumeration elements list.
RTO_IE : RX Time-out Interrupt Enable Control\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
INT_TOUT Disable
#1 : 1
INT_TOUT Enabled
End of enumeration elements list.
BUF_ERR_IE : Buffer Error Interrupt Enable Control\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
INT_BUT_ERR Disable
#1 : 1
INT_BUF_ERR Enabled
End of enumeration elements list.
WAKE_IE : Wake-up Interrupt Enable Control\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
INT_WAKE Disable
#1 : 1
INT_WAKE Enabled
End of enumeration elements list.
ABAUD_IE : Auto-baud Rate Interrupt Enable Control\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
INT_ABAUD Disable
#1 : 1
INT_ABAUD Enabled
End of enumeration elements list.
LIN_IE : LIN Interrupt Enable Control\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
INT_LIN Disable
#1 : 1
INT_LIN Enabled
End of enumeration elements list.
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