Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x30 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
LCD Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : LCD Enable Control\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
LCD controller operation Disabled
#1 : 1
LCD controller operation Enabled
End of enumeration elements list.
MUX : Mux Select \n
bits : 1 - 3 (3 bit)
access : read-write
Enumeration:
#000 : 0
Static
#001 : 1
1/2 duty
#010 : 2
1/3 duty
#011 : 3
1/4 duty
#100 : 4
1/5 duty
#101 : 5
1/6 duty
#110 : 6
Reserved
#111 : 7
Reserved
End of enumeration elements list.
FREQ : LCD Frequency Selection\n
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
#000 : 0
LCD_CLK Divided by 32
#001 : 1
LCD_CLK Divided by 64
#010 : 2
LCD_CLK Divided by 96
#011 : 3
LCD_CLK Divided by 128
#100 : 4
LCD_CLK Divided by 192
#101 : 5
LCD_CLK Divided by 256
#110 : 6
LCD_CLK Divided by 384
#111 : 7
LCD_CLK Divided by 512
End of enumeration elements list.
BLINK : LCD Blinking Enable Control\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Blinking Disabled
#1 : 1
Blinking Enabled
End of enumeration elements list.
PDDISP_EN : Power Down Display Enable Control\nThe LCD can be programmed to be displayed or not be displayed at power down state by PDDISP_EN setting.\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
LCD display Disabled ( LCD is put out) at power down state
#1 : 1
LCD display Enabled (LCD keeps the display) at power down state
End of enumeration elements list.
PDINT_EN : Power Down Interrupt Enable Control\nIf the power down request is triggered from system management, LCD controller will execute the frame completely to avoid the DC component. When the frame is executed completely, the LCD power down interrupt signal is generated to inform system management that LCD controller is ready to enter power down state, if PDINT_EN is set to 1. Otherwise, if PDINT_EN is set to 0, the LCD power down interrupt signal is blocked and the interrupt is disabled to send to system management.\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Power Down Interrupt Disabled
#1 : 1
Power Down Interrupt Enabled
End of enumeration elements list.
LCD SEG11 ~ SEG8 Data
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCD SEG15 ~ SEG12 Data
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCD SEG19 ~ SEG16 Data
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCD SEG23 ~ SEG20 Data
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCD SEG27 ~ SEG24 Data
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCD SEG31 ~ SEG28 Data
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCD SEG35 ~ SEG32 Data
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCD Frame Counter Control Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FCEN : LCD Frame Counter Enable Control\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
FCINTEN : LCD Frame Counter Interrupt Enable Control\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Frame counter interrupt Disabled
#1 : 1
Frame counter interrupt Enabled
End of enumeration elements list.
PRESCL : Frame Counter Pre-scaler Value\n
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
CLKframe/1
#01 : 1
CLKframe/2
#10 : 2
CLKframe/4
#11 : 3
CLKframe/8
End of enumeration elements list.
FCV : Frame Counter Top Value\nThese 6 bits contain the top value of the Frame counter.
bits : 4 - 9 (6 bit)
access : read-write
LCD Frame Counter Status
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FCSTS : LCD Frame Counter Status\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Frame counter value does not reach FCV (Frame Count TOP value)
#1 : 1
Frame counter value reaches FCV (Frame Count TOP value). If the FCINTEN is s enabled, the frame counter overflow Interrupt is generated
End of enumeration elements list.
PDSTS : Power-down Interrupt Status\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inform system manager that LCD controller is not ready to enter power-down state until this bit becomes 1 if power down is set and one frame is not executed completely
#1 : 1
Inform system manager that LCD controller is ready to enter power-down state if power down is set and one frame is executed completely
End of enumeration elements list.
LCD Display Control Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPUMP_EN : Charge Pump Enable Control\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BIAS_SEL : Bias Selection\n
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
#00 : 0
Static
#01 : 1
1/2 Bias
#10 : 2
1/3 Bias
#11 : 3
Reserved
End of enumeration elements list.
IBRL_EN : Internal Bias Reference Ladder Enable Control\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bias reference ladder Disabled
#1 : 1
Bias reference ladder Dnabled
End of enumeration elements list.
BV_SEL : Bias Voltage Type Selection\nNote: The external resistor ladder should be connected to the V1 pin, V2 pin, V3 pin and VSS. The VLCD pin should also be connected to VDD.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
C-Type bias mode. Bias voltage source from internal bias generator
#1 : 1
R-Type bias mode. Bias voltage source from external bias generator
End of enumeration elements list.
CPUMP_VOL_SET : Charge Pump Voltage Selection\n
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 0
2.7V
#001 : 1
2.8V
#010 : 2
2.9V
#011 : 3
3.0V
#100 : 4
3.1V
#101 : 5
3.2V
#110 : 6
3.3V
#111 : 7
3.4V
End of enumeration elements list.
CPUMP_FREQ : Charge Pump Frequency Selection\n
bits : 11 - 13 (3 bit)
access : read-write
Enumeration:
#000 : 0
LCD_CLK
#001 : 1
LCD_CLK/2
#010 : 2
LCD_CLK/4
#011 : 3
LCD_CLK/8
#100 : 4
LCD_CLK/16
#101 : 5
LCD_CLK/32
#110 : 6
LCD_CLK/64
#111 : 7
LCD_CLK/128
End of enumeration elements list.
Ext_C : Ext_C Mode Selection
This mode is similar to C-type LCD mode, but the operation current is lower than C-type mode. The control register setting is same with C-type mode except this bit is set to 1 .
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
Res_Sel : R-type Resistor Value Selection\nThe LCD operation current will be different when we select different R-type resistor value. \n
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
#00 : 0
200K Ohm
#01 : 1
300K Ohm
#10 : 2
Reserved
#11 : 3
400K Ohm
End of enumeration elements list.
LCD SEG3 ~ SEG0 Data
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEG_0_4x : For the LCD Display Memory MAP, please refer to Figure 6-54.
bits : 0 - 5 (6 bit)
access : read-write
SEG_1_4x : For the LCD Display Memory MAP, please refer to Figure 6-54.
bits : 8 - 14 (7 bit)
access : read-write
SEG_2_4x : For the LCD Display Memory MAP, please refer to Figure 6-54.
bits : 16 - 21 (6 bit)
access : read-write
SEG_3_4x : For the LCD Display Memory MAP, please refer to Figure 6-54.
bits : 24 - 29 (6 bit)
access : read-write
LCD SEG7 ~ SEG4 Data
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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