ADC_RESULT0 (RESULT0)

ADC_RESULT4 (RESULT4)

ADC_RESULT5 (RESULT5)

ADC_RESULT6 (RESULT6)

ADC_RESULT7 (RESULT7)

ADC_RESULT14 (RESULT14)

ADC_RESULT15 (RESULT15)

ADC_RESULT1 (RESULT1)

ADC_RESULT16 (RESULT16)

ADC_RESULT17 (RESULT17)

ADCR

ADCHER

ADCMPR0

ADCMPR1

ADSR

ADPDMA

ADCPWD

ADCCALCTL

ADCCALWORD

ADCCHSAMP0

ADCCHSAMP1

ADC_RESULT2 (RESULT2)

ADC_RESULT3 (RESULT3)

RSLT : A/D Conversion Result\nThis field contains 12 bits conversion results.
bits : 0 - 11 (12 bit)
access : read-only

VALID : Data Valid Flag\nAfter ADC converts finish, this field will set to high.\nThis field will clear when this register be read.
bits : 16 - 16 (1 bit)
access : read-only

OVERRUN : Over Run Flag\nWhen VALID is high and ADC converts finish, this field will set to high.
bits : 17 - 17 (1 bit)
access : read-only

ADEN : A/D Converter Enable Control\nBefore starting A/D conversion, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit power consumption.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADIE : A/D Interrupt Enable Control\nA/D conversion end interrupt request is generated if ADIE bit is set to 1.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADMD : A/D Converter Operation Mode\n
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRGS : Hardware Trigger Source\nSoftware should disable TRGE and ADST before change TRGS. \nIn hardware trigger mode, the ADST bit is set by the external trigger from STADC or PWM trigger, However software has the highest priority to set or cleared ADST bit at any time.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRGCOND : External Trigger Condition\nThese two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state.\n
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRGEN : External Trigger Enable Control\nEnable or disable triggering of A/D conversion by external STADC pin.\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PTEN : PDMA Transfer Enable Control\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DIFF : Differential Mode Selection\nNote: Calibration should calibrated each time when switching between single-ended and differential mode
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADST : A/D Conversion Start\nADST bit can be set to 1 from three sources: software write, external pin STADC and PWM trigger. ADST is cleared to 0 by hardware automatically at the end of single mode and single-cycle scan mode on specified channels. In continuous scan mode, A/D conversion is continuously performed sequentially unless software writes 0 to this bit or chip reset.\nNote: After ADC conversion done, SW needs to wait at least one ADC clock before to set this bit high again.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMSEL : Select A/D Enable Time-out Source \n
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMTRGMOD : Timer Event Trigger ADC Conversion\nsetting TMSEL to select timer event from timer0~3
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REFSEL : Reference Voltage Source Selection\n
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RESSEL : Resolution Selection\n
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMPDMACNT : PDMA Count\nWhen each timer event occur PDMA will transfer TMPDMACNT +1 ADC result in the amount of this register setting\nNote: The total amount of PDMA transferring data should be set in PDMA byte count register. When PDMA finish is set, ADC will not be enabled and start transfer even though the timer event occurred
bits : 24 - 31 (8 bit)
access : read-write

CHEN0 : Analog Input Channel 0 Enable Control (Convert Input Voltage From PA.0 )\nIf more than one channel in single mode is enabled by software, the least channel is converted and other enabled channels will be ignored.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN1 : Analog Input Channel 1 Enable Control (Convert Input Voltage From PA.1 )\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN2 : Analog Input Channel 2 Enable Control (Convert Input Voltage From PA.2 )\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN3 : Analog Input Channel 3 Enable Control (Convert Input Voltage From PA.3 )\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN4 : Analog Input Channel 4 Enable Control (Convert Input Voltage From PA.4 )\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN5 : Analog Input Channel 5 Enable Control (Convert Input Voltage From PA.5 )\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN6 : Analog Input Channel 6 Enable Control (Convert Input Voltage From PA.6 )\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN7 : Analog Input Channel 7 Enable Control (Convert Input Voltage From PA.7 )\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN14 : Analog Input Channel 14 Enable Control (Convert VTEMP)\n
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN15 : Analog Input Channel 15 Enable Control (Convert Int_VREF)\n
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN16 : Analog Input Channel 16 Enable Control (Convert AVDD)\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN17 : Analog Input Channel 17 Enable Control (Convert AVSS)
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPEN : Compare Enable Control\nSet this bit to 1 to enable compare CMPD[11:0] with specified channel conversion result when converted data is loaded into ADC_RESULTx register.\nWhen this bit is set to 1, and CMPMATCNT is 0, the CMPF will be set once the match is hit.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPIE : Compare Interrupt Enable Control\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPF bit will be asserted, in the meanwhile, if CMPIE is set to 1, a compare interrupt request is generated.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPCOND : Compare Condition\nNote: When the internal counter reaches the value to (CMPMATCNT +1), the CMPF bit will be set.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPCH : Compare Channel Selection\nSet this field to select which channel's result to be compared.\nNote: Valid setting of this field is channel 0~17, but channel 8~14 are reserved.
bits : 3 - 7 (5 bit)
access : read-write

CMPMATCNT : Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2], the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPF bit will be set.
bits : 8 - 11 (4 bit)
access : read-write

CMPD : Comparison Data\nThe 12 bits data is used to compare with conversion result of specified channel. Software can use it to monitor the external analog input pin voltage variation in scan mode without imposing a load on software.
bits : 16 - 27 (12 bit)
access : read-write

ADF : A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion.\nADF is set to 1 at these two conditions:\nWhen A/D conversion ends in single mode\nWhen A/D conversion ends on all specified channels in scan mode.\nThis flag can be cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write

CMPF0 : Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR0 then this bit is set to 1. And it is cleared by writing 1 to self.\nThis flag can be cleared by writing 1 to it.\nNote: When this flag is set, the matching counter will be reset to 0,and continue to count when user write 1 to clear CMPF0
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPF1 : Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR1 then this bit is set to 1. And it is cleared by writing 1 to self.\nThis flag can be cleared by writing 1 to it.\nNote: When this flag is set, the matching counter will be reset to 0,and continue to count when user writes 1 to clear CMPF1.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUSY : BUSY/IDLE (Read Only)\n
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CHANNEL : Current Conversion Channel (Read Only)\n
bits : 4 - 8 (5 bit)
access : read-only

INITRDY : ADC Power-up Sequence Completed\nNote: This bit will be set after system reset occurred and automatically cleared by power-up event.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AD_PDMA : ADC PDMA Current Transfer Data (Read Only)\nWhen PDMA transferring, reading these bits can monitor the current PDMA transfer data.
bits : 0 - 11 (12 bit)
access : read-only

PWUPRDY : ADC Power-up Sequence Completed and Ready for Conversion\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWDCALEN : Power Up Calibration Function Enable Control Note: This bit work together with CALSEL (ADCCALCTL[3]), see the following {PWDCALEN,CALFBSEL} Description: PWDCALEN is 0 and CALFBSEL is 0: No need to calibrate. PWDCALEN is 0 and CALFBSEL is 1: No need to calibrate. PWDCALEN is 1 and CALFBSEL is 0: Load calibration word when power up. PWDCALEN is 1 and CALFBSEL is 1: Calibrate when power up.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWDMOD : ADC Power-down Mode Set this bit fields to select ADC Power-down mode when system power-down. Note1: Different PWDMOD has different power down/up sequence, in order to avoid ADC powering up with wrong sequence user must keep PWMOD consistent each time in power down and power up. Note2: While the ADC is power up from Power-down mode without calibration, the PWDCALEN(ADCPWD[1]) is set to 0. (The calibration value will be reset)
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CALEN : Calibration Function Enable Control\nEnable this bit to turn on the calibration function block.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CALSTART : Calibration Functional Block Start\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CALDONE : Calibrate Functional Block Complete\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CALSEL : Select Calibration Functional Block\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CALWORD : Calibration Word Bits Write to this register with the previous calibration word before load calibration action Read this register after calibration done Note: The calibration block contains two parts CALIBRATION and LOAD CALIBRATION if the calibration block configure as CALIBRATION then this register represent the result of calibration when calibration is completed if configure as LOAD CALIBRATION configure this register before loading calibration action, after loading calibration complete, the laoded calibration word will apply to the ADC while in loading calibration function the loaded value will not be equal to the original CALWORD until calibration is done.
bits : 0 - 6 (7 bit)
access : read-write

CH0SAMPCNT : Channel 0 Sampling Counter CH0SAMPCNT ADC Clock
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH1SAMPCNT : Channel 1 Sampling Counter\nThe same as Channel 0 sampling counter table.
bits : 4 - 7 (4 bit)
access : read-write

CH2SAMPCNT : Channel 2 Sampling Counter\nThe same as Channel 0 sampling counter table.
bits : 8 - 11 (4 bit)
access : read-write

CH3SAMPCNT : Channel 3 Sampling Counter\nThe same as Channel 0 sampling counter table.
bits : 12 - 15 (4 bit)
access : read-write

CH4SAMPCNT : Channel 4 Sampling Counter\nThe same as Channel 0 sampling counter table.
bits : 16 - 19 (4 bit)
access : read-write

CH5SAMPCNT : Channel 5 Sampling Counter\nThe same as Channel 0 sampling counter table.
bits : 20 - 23 (4 bit)
access : read-write

CH6SAMPCNT : Channel 6 Sampling Counter\nThe same as Channel 0 sampling counter table.
bits : 24 - 27 (4 bit)
access : read-write

CH7SAMPCNT : Channel 7 Sampling Counter\nThe same as Channel 0 sampling counter table.
bits : 28 - 31 (4 bit)
access : read-write

INTCHSAMPCNT : Internal Channel (VTEMP, AVDD, AVSS, Int_VREF) Sampling Counter\nThe same as Channel 0 sampling counter table.
bits : 16 - 19 (4 bit)
access : read-write