\n
address_offset : 0x0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x50 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x40 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
ISP Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPEN : ISP Enable Bit (Write Protect)\nSet this bit to enable ISP function.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
ISP function Disabled
#1 : 1
ISP function Enabled
End of enumeration elements list.
BS : Boot Select (Write Protect)\nSet/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS in CONFIG0 after any reset is happened except CPU reset (CPURF is 1) or system reset (SYSRF) is happened.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Boot from APROM
#1 : 1
Boot from LDROM
End of enumeration elements list.
SPUEN : SPROM Update Enable Bit (Write Protect)
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPROM cannot be updated
#1 : 1
SPROM can be updated when the MCU runs in APROM
End of enumeration elements list.
APUEN : APROM Update Enable Bit (Write Protect)
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
APROM cannot be updated when chip runs in APROM
#1 : 1
APROM can be updated when chip runs in APROM
End of enumeration elements list.
CFGUEN : CONFIG Update Enable Bit (Write Protect)\nWriting this bit to 1 enables software to update CONFIG value by ISP register control procedure regardless of program code is running in APROM or LDROM.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
ISP update User Configuration Disabled
#1 : 1
ISP update User Configuration Enabled
End of enumeration elements list.
LDUEN : LDROM Update Enable Bit (Write Protect)
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
LDROM cannot be updated
#1 : 1
LDROM can be updated when the MCU runs in APROM
End of enumeration elements list.
ISPFF : ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) SPROM writes to itself if SPUEN is set to 0.\n(4) CONFIG is erased/programmed if CFGUEN is set to 0.\n(5) Destination address is illegal, such as over an available range.\nNote: Write 1 to clear this bit to 0.
bits : 6 - 6 (1 bit)
access : read-write
ISP Trigger Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPGO : ISP Start Trigger (Write Protect)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
ISP operation is finished
#1 : 1
ISP operation is progressed
End of enumeration elements list.
Data Flash Start Address
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DFBA : Data Flash Base Address\nThis register indicates Data Flash start address. It is a read only register.\nThe Data Flash start address is defined by user. Since on chip Flash erase unit is 512 bytes, it is mandatory to keep bit 8-0 as 0.
bits : 0 - 31 (32 bit)
access : read-only
ISP Address Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPADR : ISP Address\nThe NDA102 series supports word program only. ISPADR[1:0] must be kept 00 for ISP operation.
bits : 0 - 31 (32 bit)
access : read-write
ISP Status Register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPBUSY : ISP Start Trigger (Read Only)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nNote: This bit is the same with FMC_ISPTRG bit 0.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
ISP operation is finished
#1 : 1
ISP operation is progressed
End of enumeration elements list.
CBS : Config Boot Selection (Read Only)\nThis is a mirror of CBS in CONFIG0.
bits : 1 - 2 (2 bit)
access : read-only
ISPFF : ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) SPROM writes to itself if SPUEN is set to 0.\n(4) CONFIG is erased/programmed if CFGUEN is set to 0.\n(5) Destination address is illegal, such as over an available range.\nNote: Write 1 to clear this bit to 0.
bits : 6 - 6 (1 bit)
access : read-write
VECMAP : Vector Page Mapping Address (Read Only)\nThe current Flash address space 0x0000_0000~0x0000_01FF is mapping to address {VECMAP[11:0], 9'h000} ~ {VECMAP[11:0], 9'h1FF}.
bits : 9 - 20 (12 bit)
access : read-only
SCODE : Security Code Active Flag
This bit field set by hardware when detecting SPROM secured code is active at Flash initiation, or software writes 1 to this bit to make secured code active this bit is clear by SPROM page erase operation.
bits : 29 - 31 (3 bit)
access : read-write
Enumeration:
#000 : 0
SPROM0/1/2 secured code are inactive
#001 : 1
SPROM0 secured code is active
#010 : 2
SPROM1 secured code is active
#100 : 4
SPROM2 secured code is active
#111 : 7
SPROM0/1/2 Secured code are active
End of enumeration elements list.
ISP CRC Seed Register
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRCSEED : CRC Seed Data\nThis register was provided to be the initial value for CRC operation.\nWrite data to this register before ISP CRC operation.\nRead data from this register after ISP CRC read operation.
bits : 0 - 31 (32 bit)
access : read-write
ISP CRC Current Value Register
address_offset : 0x54 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CRCCV : CRC Current Value\nThis register provided current value of CRC durning calculation.
bits : 0 - 31 (32 bit)
access : read-only
ISP Data Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPDAT : ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation.
bits : 0 - 31 (32 bit)
access : read-write
ISP Command Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : ISP Command \nISP commands are shown below:
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0x00 : 0
Read
0x04 : 4
Read Unique ID
0x0b : 11
Read Company ID (0xDA)
0x0d : 13
Read CRC32 Checksum Result After Calculating
0x21 : 33
Program
0x22 : 34
Page Erase
0x2d : 45
Run Memory CRC32 Checksum Calculation
0x2e : 46
Set Vector Page Re-Map
End of enumeration elements list.
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