EPWM_NPCTL (NPCTL)

EPWM_CMPDAT0 (CMPDAT0)

EPWM_CMPDAT1 (CMPDAT1)

EPWM_CMPDAT2 (CMPDAT2)

EPWM_CMPDAT3 (CMPDAT3)

EPWM_CMPDAT4 (CMPDAT4)

EPWM_CMPDAT5 (CMPDAT5)

EPWM_CNT (CNT)

EPWM_CLKDIV (CLKDIV)

EPWM_INTEN (INTEN)

EPWM_INTSTS (INTSTS)

EPWM_RESDLY (RESDLY)

EPWM_BRKCTL (BRKCTL)

EPWM_DTCTL (DTCTL)

EPWM_PHCHG (PHCHG)

EPWM_PHCHGNXT (PHCHGNXT)

EPWM_CTL (CTL)

EPWM_PHCHGALT (PHCHGALT)

EPWM_IFA (IFA)

EPWM_PERIOD (PERIOD)

NEGPOLAR0 : PWM0 Negative Polarity Control\nThe register bit controls polarity/active state of real PWM output.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

NEGPOLAR1 : PWM1 Negative Polarity Control\nThe register bit controls polarity/active state of real PWM output.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

NEGPOLAR2 : PWM2 Negative Polarity Control\nThe register bit controls polarity/active state of real PWM output.\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

NEGPOLAR3 : PWM3 Negative Polarity Control\nThe register bit controls polarity/active state of real PWM output.\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

NEGPOLAR4 : PWM4 Negative Polarity Control\nThe register bit controls polarity/active state of real PWM output.\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

NEGPOLAR5 : PWM5 Negative Polarity Control\nThe register bit controls polarity/active state of real PWM output.\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMP : PWM Comparator Register CMP determines the PWM Duty. Edge-aligned mode: where xy, could be 01, 23, 45 depending on the selected PWM channel. Note: Any write to CMPn will take effect in next PWM cycle.
bits : 0 - 15 (16 bit)
access : read-write

CMPU : PWM Comparator Register for UP Counter in Center-aligned Asymmetric Mode CMPU PERIOD: @ up counter PWM output is keep to Max. duty.
bits : 16 - 31 (16 bit)
access : read-write

CNT : PWM Data Register\nUser can monitor CNT to know the current value in 16-bit down counter.
bits : 0 - 15 (16 bit)
access : read-only

CNTDIR : PWM Counter (Up/Down) Direction\n
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CLKDIV : EPWM Clock Divider (9 Step Divider)\nSelect clock input for PWM timer\n
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PIEN : PWM Channel 0 Period Interrupt Enable Control\nfor Edge-aligned and Center-aligned \n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPUIEN0 : PWM Channel 0 UP Interrupt Enable Control\nUP for Center-aligned only\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPUIEN1 : PWM Channel 1 UP Interrupt Enable Control\nUP for Center-aligned only\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPUIEN2 : PWM Channel 2 UP Interrupt Enable Control\nUP for Center-aligned only\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPUIEN3 : PWM Channel 3 UP Interrupt Enable Control\nUP for Center-aligned only\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPUIEN4 : PWM Channel 4 UP Interrupt Enable Control\nUP for Center-aligned only\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPUIEN5 : PWM Channel 5 UP Interrupt Enable Control\nUP for Center-aligned only\n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRK0IEN : Fault Brake0 Interrupt Enable Control\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRK1IEN : Fault Brake1 Interrupt Enable Control\n
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CIEN : PWM Central Interrupt Enable Control\nfor Center-aligned only \n
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPDIEN0 : PWM Channel 0 DOWN Interrupt Enable Control\nDOWN for Edge-aligned and Center-aligned\n
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPDIEN1 : PWM Channel 1 DOWN Interrupt Enable Control\nDOWN for Edge-aligned and Center-aligned\n
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPDIEN2 : PWM Channel 2 DOWN Interrupt Enable Control\nDOWN for Edge-aligned and Center-aligned\n
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPDIEN3 : PWM Channel 3 DOWN Interrupt Enable Control\nDOWN for Edge-aligned and Center-aligned\n
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPDIEN4 : PWM Channel 4 DOWN Interrupt Enable Control\nDOWN for Edge-aligned and Center-aligned\n
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPDIEN5 : PWM Channel 5 DOWN Interrupt Enable Control\nDOWN for Edge-aligned and Center-aligned\n
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PIF : PWM Channel 0 Period Interrupt Flag\nEdge-aligned mode:\nFlag is set by hardware when PWM down counter reaches zero point. \nCenter-aligned mode:\nFlag is set by hardware when PWM down counter reaches zero point and then up counter reaches EPWM_PERIOD.\nSoftware can write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write

CMPUIF0 : PWM Channel 0 UP Interrupt Flag\nFlag is set by hardware when a channel 0 PWM UP counter reaches PWM_CMPDAT0. Software can write 1 to clear this bit.
bits : 8 - 8 (1 bit)
access : read-write

CMPUIF1 : PWM Channel 1 UP Interrupt Flag\nFlag is set by hardware when a channel 1 PWM UP counter reaches PWM_CMPDAT1. Software can write 1 to clear this bit.
bits : 9 - 9 (1 bit)
access : read-write

CMPUIF2 : PWM Channel 2 UP Interrupt Flag\nFlag is set by hardware when a channel 2 PWM UP counter reaches PWM_CMPDAT2. Software can write 1 to clear this bit.
bits : 10 - 10 (1 bit)
access : read-write

CMPUIF3 : PWM Channel 3 UP Interrupt Flag\nFlag is set by hardware when a channel 3 PWMUP counter reaches PWM_CMPDAT3. Software can write 1 to clear this bit.
bits : 11 - 11 (1 bit)
access : read-write

CMPUIF4 : PWM Channel 4 UP Interrupt Flag\nFlag is set by hardware when a channel 4 PWM UP counter reaches PWM_CMPDAT4. Software can write 1 to clear this bit.
bits : 12 - 12 (1 bit)
access : read-write

CMPUIF5 : PWM Channel 5 UP Interrupt Flag\nFlag is set by hardware when a channel 5 PWM UP counter reaches PWM_CMPDAT5. Software can write 1 to clear this bit.
bits : 13 - 13 (1 bit)
access : read-write

BRK0IF : PWM Brake0 Flag\nNote: Software can write 1 to clear this bit.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRK1IF : PWM Brake1 Flag\nNote: Software can write 1 to clear this bit.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CIF : PWM Channel 0 Central Interrupt Flag\nFlag is set by hardware when PWM down counter reaches zero point. Software can write 1 to clear this bit.
bits : 18 - 18 (1 bit)
access : read-write

CMPDIF0 : PWM Channel 0 DOWN Interrupt Flag\nFlag is set by hardware when a channel 0 PWM DOWN counter reaches EPWM_CMPDAT0. Software can write 1 to clear this bit.
bits : 24 - 24 (1 bit)
access : read-write

CMPDIF1 : PWM Channel 1 DOWN Interrupt Flag\nFlag is set by hardware when a channel 1 PWM DOWN counter reaches EPWM_CMPDAT1. Software can write 1 to clear this bit.
bits : 25 - 25 (1 bit)
access : read-write

CMPDIF2 : PWM Channel 2 DOWN Interrupt Flag\nFlag is set by hardware when a channel 2 PWM DOWN counter reaches EPWM_CMPDAT2. Software can write 1 to clear this bit.
bits : 26 - 26 (1 bit)
access : read-write

CMPDIF3 : PWM Channel 3 DOWN Interrupt Flag\nFlag is set by hardware when a channel 3 PWM DOWN counter reaches EPWM_CMPDAT3. Software can write 1 to clear this bit.
bits : 27 - 27 (1 bit)
access : read-write

CMPDIF4 : PWM Channel 4 DOWN Interrupt Flag\nFlag is set by hardware when a channel 4 PWM DOWN counter reaches EPWM_CMPDAT4. Software can write 1 to clear this bit.
bits : 28 - 28 (1 bit)
access : read-write

CMPDIF5 : PWM Channel 5 DOWN Interrupt Flag\nFlag is set by hardware when a channel 5 PWM DOWN counter reaches EPWM_CMPDAT5. Software can write 1 to clear this bit.
bits : 29 - 29 (1 bit)
access : read-write

DELAY : PWM BRK Low Voltage Detect Resume Delay\n12 bits Down-Counter
bits : 0 - 11 (12 bit)
access : read-write

BRK0EN : Brake0 Function Enable Control\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRK1EN : Brake1 Function Enable Control\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRK0A0EN : BRK0 Source From ACMP0 Enable Control\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRK0A1EN : BRK0 Source From ACMP1 Enable Control\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BK0ADCEN : BRK0 Source From ADC Enable Control\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRK0PEN : BRK0 Source From External Pin Enable Control\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SWBRK : Software Break\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRK1A0EN : BRK1 Source From ACMP0 Enable Control\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRK1A1EN : BRK1 Source From ACMP1 Enable Control\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BK1ADCEN : BRK1 Source From ADC Enable Control\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRK1PEN : BRK1 Source From External Pin Enable Control\n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVDBKEN : Low-level Detection Trigger PWM Brake Function 1 Enable Control\n
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVDTYPE : Low-level Detection Resume Type\n
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BKOD0 : PWM Channel 0 Brake Output Selection\n
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BKOD1 : PWM Channel 1 Brake Output Selection\n
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BKOD2 : PWM Channel 2 Brake Output Selection\n
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BKOD3 : PWM Channel 3 Brake Output Selection\n
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BKOD4 : PWM Channel 4 Brake Output Selection\n
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BKOD5 : PWM Channel 5 Brake Output Selection\n
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

NFPEN : Noise Filter for External Brake Input Pin (BRAKE) Enable Control\n
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DTCNT01 : Dead-zone Interval Register for Pair of Channel0 and Channel1 (PWM0 and PWM1 Pair)\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding EPWM_CLKDIV bits.
bits : 0 - 7 (8 bit)
access : read-write

DTCNT23 : Dead-zone Interval Register for Pair of Channel2 and Channel3 (PWM2 and PWM3 Pair)\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding EPWM_CLKDIV bits.
bits : 8 - 15 (8 bit)
access : read-write

DTCNT45 : Dead-zone Interval Register for Pair of Channel4 and Channel5 (PWM4 and PWM5 Pair)\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding EPWM_CLKDIV bits.
bits : 16 - 23 (8 bit)
access : read-write

MSKDAT0 : Enable PWM0 Mask Data\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKDAT1 : Enable PWM1 Mask Data\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKDAT2 : Enable PWM2 Mask Data\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKDAT3 : Enable PWM3 Mask Data\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKDAT4 : Enable PWM4 Mask Data\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKDAT5 : Enable PWM5 Mask Data\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKEN0 : Enable PWM0 Mask Function\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKEN1 : Enable PWM1 Mask Function\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKEN2 : Enable PWM2 Mask Function\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKEN3 : Enable PWM3 Mask Function\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKEN4 : Enable PWM4 Mask Function\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKEN5 : Enable PWM5 Mask Function\n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRGSEL : Phase Change Trigger Selection\nSelect the trigger condition to load PHCHG from PHCHG_NXT.\nWhen the trigger condition occurs it will load PHCHG_NOW with PHCHG_NXT.\nPhase Change: PWM outputs are masked according with the definition of MSKENn and MSKDATn in PHCHG_NOW.\n
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

A0POSSEL : Alternative Comparator 0 Positive Input Selection\nSelect the positive input source of ACMP0.\n
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

A1POSSEL : Alternative Comparator 1 Positive Input Selection\nSelect the positive input source of ACMP1.\n
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACMP0TEN : ACMP0 Trigger Function Enable Control\n
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACMP1TEN : ACMP1 Trigger Function Enable Control\n
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSKDAT0 : Enable PWM0 Mask Data Preset Bit\nThis bit will be load to bit MSKDAT0 in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
bits : 0 - 0 (1 bit)
access : read-write

MSKDAT1 : Enable PWM1 Mask Data Preset Bit\nThis bit will be load to bit MSKDAT1 in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
bits : 1 - 1 (1 bit)
access : read-write

MSKDAT2 : Enable PWM2 Mask Data Preset Bit\nThis bit will be load to bit MSKDAT2 in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
bits : 2 - 2 (1 bit)
access : read-write

MSKDAT3 : Enable PWM3 Mask Data Preset Bit\nThis bit will be load to bit MSKDAT3 in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
bits : 3 - 3 (1 bit)
access : read-write

MSKDAT4 : Enable PWM4 Mask Data Preset Bit\nThis bit will be load to bit MSKDAT4 in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
bits : 4 - 4 (1 bit)
access : read-write

MSKDAT5 : Enable PWM5 Mask Data Preset Bit\nThis bit will be load to bit MSKDAT5 in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
bits : 5 - 5 (1 bit)
access : read-write

MSKEN0 : Enable PWM0 Mask Function Preset Bit\nThis bit will be load to bit MSKEN0 in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
bits : 8 - 8 (1 bit)
access : read-write

MSKEN1 : Enable PWM1 Mask Function Preset Bit\nThis bit will be load to bit MSKEN1 in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
bits : 9 - 9 (1 bit)
access : read-write

MSKEN2 : Enable PWM2 Mask Function Preset Bit\nThis bit will be load to bit MSKEN2 in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
bits : 10 - 10 (1 bit)
access : read-write

MSKEN3 : Enable PWM3 Mask Function Preset Bit\nThis bit will be load to bit MSKEN3 in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
bits : 11 - 11 (1 bit)
access : read-write

MSKEN4 : Enable PWM4 Mask Function Preset Bit\nThis bit will be load to bit MSKEN4 in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
bits : 12 - 12 (1 bit)
access : read-write

MSKEN5 : Enable PWM5 Mask Function Preset Bit\nThis bit will be load to bit MSKEN5 in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
bits : 13 - 13 (1 bit)
access : read-write

HALLSTS : Predicted Next HALL State\nThis bit field indicates the predicted hall state at next commutation. \nthe hardware will compare bits (CAP2, CAP1, CAP0) in timer 2 with HALLSTS [2:0] when any hall state change occurs.\nIf the comparison is matched it will trigger phase change function.
bits : 16 - 18 (3 bit)
access : read-write

TRGSEL : Phase Change Trigger Selection Preset Bits\nThis bit field will be load to bit field TRGSEL in PHCHG_NOW when load trigger condition occurs.\nRefer to register EPWM_PHCHG for detailed definition.
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

A0POSSEL : Alternative Comparator 0 Positive Input Selection Preset Bits\nThis bit field will be load to bit field A0POSSEL in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
bits : 24 - 25 (2 bit)
access : read-write

A1POSSEL : Alternative Comparator 1 Positive Input Selection Preset Bits\nThis bit field will be load to bit field A1POSSEL in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
bits : 26 - 27 (2 bit)
access : read-write

ACMP0TEN : ACMP0 Trigger Function Control Preset Bit\nThis bit will be load to bit ACMP0TEN in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
bits : 28 - 28 (1 bit)
access : read-write

ACMP1TEN : ACMP1 Trigger Function Control Preset Bit\nThis bit will be load to bit ACMP1TEN in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition.
bits : 29 - 29 (1 bit)
access : read-write

CNTEN0 : PWM-timer 0 Enable/Disable Start Run\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTEN1 : PWM-timer 1 Enable/Disable Start Run\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTEN2 : PWM-timer 2 Enable/Disable Start Run\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTEN3 : PWM-timer 3 Enable/Disable Start Run\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTEN4 : PWM-timer 4 Enable/Disable Start Run\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTEN5 : PWM-timer 5 Enable/Disable Start Run\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTMODE : PWM-timer Auto-reload/One-shot Mode\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HCUPDT : Half Cycle Update Enable for Center-aligned Type\n
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ASYMEN : Asymmetric Mode in Center-aligned Type \n
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBGTRIOFF : PWM Debug Mode Configuration Bit (Available in DEBUG Mode Only)\n
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DTCNT01 : Dead-zone 0 Generator Enable/Disable (PWM0 and PWM1 Pair for PWM Group)\nNote: When the dead-zone generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair for PWM group.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DTCNT23 : Dead-zone 2 Generator Enable/Disable (PWM2 and PWM3 Pair for PWM Group)\nNote: When the dead-zone generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair for PWM group.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DTCNT45 : Dead-zone 4 Generator Enable/Disable (PWM4 and PWM5 Pair for PWM Group)\nNote: When the dead-zone generator is enabled, the pair of PWM4 and PWM5 becomes a complementary pair for PWM group.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTCLR : Clear PWM Counter Control Bit\nNote: It is automatically cleared by hardware.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE : PWM Operating Mode Selection\n
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GROUPEN : Group Bit\n
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTTYPE : PWM Aligned Type Selection\n
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

POSCTL0 : Positive Input Control for ACMP0\nNote: Register ACMP_CTL0 is describe in Comparator Controller chapter
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

POSCTL1 : Positive Input Control for ACMP1\nNote: Register ACMP_CTL1 is describe in Comparator Controller chapter
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IFAEN : Enable Period Interrupt Accumulation Function\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IFCNT : Period Interrupt Accumulation Counter Value Setting Register (Write Only)\n16 step Down-Counter value setting register.\nWhen IFAEN is set, IFCNT value will load into IFDAT and decrase gradually.
bits : 4 - 7 (4 bit)
access : write-only

IFDAT : Period Interrupt Down-counter Data Register (Read Only)\nWhen IFAEN is set, IFDAT will decrease when every PWM Interrupt flag is set,\n and when IFDAT reaches 0, the PWM interrupt will occurred and IFCNT will reload to IFDAT.
bits : 12 - 15 (4 bit)
access : read-only

PERIOD : PWM Counter/Timer Loaded Value PERIODn determines the PWM Period. Edge-aligned mode: where xy, could be 01, 23, 45 depending on the selected PWM channel. Note: Any write to PERIODn will take effect in next PWM cycle.
bits : 0 - 15 (16 bit)
access : read-write