\n

ADC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x20 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected

Registers

ADC_DAT0 (DAT0)

ADC_CTL (CTL)

ADC_TRGSOR (TRGSOR)

ADC_TRGDLY (TRGDLY)

ADC_SMPCNT (SMPCNT)

ADC_STATUS (STATUS)

ADC_WCMPCTL (WCMPCTL)

ADC_WCMPDAT (WCMPDAT)

ADC_DAT1 (DAT1)


ADC_DAT0 (DAT0)

ADC data register 0
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ADC_DAT0 ADC_DAT0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC0DAT0 ADC0OV ADC0VALID ADC1DAT0 ADC1OV ADC1VALID

ADC0DAT0 : ADC0 Conversion Result\nThis field contains conversion result of ADC.
bits : 0 - 11 (12 bit)
access : read-only

ADC0OV : ADC0 over Run Flag Note1: If converted data in ADC0DAT0[11:0] has not been read before the new conversion result is loaded to this register, OV is set to 1 . Note2: It is cleared by hardware after the ADC_DAT0 register is read.
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

#0 : 0

Data in ADC0DAT0[11:0] is recent conversion result

#1 : 1

Data in ADC0DAT0[11:0] overwritten

End of enumeration elements list.

ADC0VALID : ADC0 Valid Flag Note: This bit is set to 1 when A/D conversion is completed and cleared by hardware after the ADC_DAT0 register is read.
bits : 15 - 15 (1 bit)
access : read-only

Enumeration:

#0 : 0

Data in ADC0DAT0[11:0] bits not valid

#1 : 1

Data in ADC0DAT0[11:0] bits valid

End of enumeration elements list.

ADC1DAT0 : ADC1 Conversion Result\nThis field contains conversion result of ADC.
bits : 16 - 27 (12 bit)
access : read-only

ADC1OV : ADC1 over Run Flag Note1: If converted data in ADC1DAT0[27:16] has not been read before, the new conversion result is loaded to this register, OV is set to 1 . Note2:It is cleared by hardware after the ADC_DAT0 register is read.
bits : 30 - 30 (1 bit)
access : read-only

Enumeration:

#0 : 0

Data in ADC1DAT0[27:16] is recent conversion result

#1 : 1

Data in ADC1DAT0[27:16] overwritten

End of enumeration elements list.

ADC1VALID : ADC1 Valid Flag Note: This bit is set to 1 when A/D conversion is completed and cleared by hardware after the ADC_DAT0 register is read.
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

#0 : 0

Data in ADC1DAT0[27:16] bits not valid

#1 : 1

Data in ADC1DAT0[27:16] bits valid

End of enumeration elements list.


ADC_CTL (CTL)

ADC Control Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_CTL ADC_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCEN ADC0IEN ADC0HWTRGEN ADC0SWTRG ADCSS3R ADCMODE ADC1IEN ADC1HWTRGEN ADC1SWTRG ADC0CHSEL ADC0SEQSEL ADC1CHSEL ADC1SEQSEL

ADCEN : ADC Converter Enable Note: Before starting the A/D conversion function, this bit should be set to 1 . Clear it to 0 to disable A/D converter analog circuit power consumption.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

ADC Converter Disabled

#1 : 1

ADC Converter Enabled

End of enumeration elements list.

ADC0IEN : ADC0 Interrupt Enable Note: A/D conversion end interrupt request is generated if ADC0IEN bit is set to 1 .
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

ADC0 interrupt function Disabled

#1 : 1

ADC0 interrupt function Enabled

End of enumeration elements list.

ADC0HWTRGEN : Hardware Trigger ADC Convertion Enable\nEnable or disable triggering of A/D conversion by Hardware (PWM, Timer, ADC self)\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

ADC0SWTRG : ADC0 Conversion Start Note: ADC0SWTRG can be set to 1 from two sources: software and external pin STADC. This bit will be cleared to 0 by hardware automatically.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Conversion stopped and A/D converter entered idle state

#1 : 1

Conversion start

End of enumeration elements list.

ADCSS3R : None
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

convert sequential is ADC0 - ADC1 - ADC0 - ADC1, four datas at ADCMODE=11

#1 : 1

convert sequential is ADC0 - ADC1 - ADC0, three datas at ADCMODE=11

End of enumeration elements list.

ADCMODE : A/D Conversion Mode\n
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

#00 : 0

Independent simple independent function and independent interrupt by themselves

#01 : 1

Independent 2SH independent trigger function, ADC0 with ADC1 both convert finish then only generate interrupt ADC0IF

#10 : 2

Simultaneous Simple simultaneous trigger function by ADC0, ADC0 with ADC1 both convert finish then generate interrupt ADC0IF

#11 : 3

Simultaneous Sequential simultaneous trigger function by ADC0, this mode converts sequential is ADC0 - ADC1 - ADC0 - ADC1 4 times, then generate interrupt ADC0IF

End of enumeration elements list.

ADC1IEN : ADC1 Interrupt Enable Control Note: A/D conversion end interrupt request is generated if ADC1IEN bit is set to 1 .
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

ADC1 interrupt function Disabled

#1 : 1

ADC1 interrupt function Enabled

End of enumeration elements list.

ADC1HWTRGEN : Hardware Trigger ADC Convertion Enable Control\nEnable or disable triggering of A/D conversion by Hardware (PWM, Timer, ADC self)\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Hardware Trigger ADC Convertion Disabled

#1 : 1

Hardware Trigger ADC Convertion Enabled

End of enumeration elements list.

ADC1SWTRG : ADC1 Conversion Start Note: ADC1SWTRG can be set to 1 from two sources: software and external pin STADC. This bit will be cleared to 0 by hardware automatically.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Conversion stopped and A/D converter entered idle state

#1 : 1

Conversion start

End of enumeration elements list.

ADC0CHSEL : ADC1 Channel Select
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

#000 : 0

ADC0_CH0

#001 : 1

ADC0_CH1

#010 : 2

ADC0_CH2

#011 : 3

ADC0_CH3

#100 : 4

ADC0_CH4

#101 : 5

PGA_ADC

#110 : 6

BAND_GAP

#111 : 7

VSS

End of enumeration elements list.

ADC0SEQSEL : ADC0 Sequential Input Pin Selection\n
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

#000 : 0

ADC0_CH0

#001 : 1

ADC0_CH1

#010 : 2

ADC0_CH2

#011 : 3

ADC0_CH3

#100 : 4

ADC0_CH4

#101 : 5

PGA_ADC

#110 : 6

BAND_GAP

#111 : 7

VSS

End of enumeration elements list.

ADC1CHSEL : ADC1 Channel Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

#000 : 0

ADC1_CH0

#001 : 1

ADC1_CH1

#010 : 2

ADC1_CH2

#011 : 3

ADC0_CH0

#100 : 4

ADC0_CH4

#101 : 5

PGA_ADC

#110 : 6

Temp Sensor

#111 : 7

VSS

End of enumeration elements list.

ADC1SEQSEL : ADC1 Sequential Input Pin Selection (Second Input)\n
bits : 28 - 30 (3 bit)
access : read-write

Enumeration:

#000 : 0

ADC1_CH0

#001 : 1

ADC1_CH1

#010 : 2

ADC1_CH2

#011 : 3

ADC0_CH0

#100 : 4

ADC0_CH4

#101 : 5

PGA_ADC

#110 : 6

Temp Sensor

#111 : 7

VSS

End of enumeration elements list.


ADC_TRGSOR (TRGSOR)

ADC Hardware Trigger Source Control Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_TRGSOR ADC_TRGSOR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC0TRGSOR ADC0PWMTRGSEL ADC0STADCSEL ADC1TRGSOR ADC1PWMTRGSEL ADC1STADCSEL

ADC0TRGSOR : ADC0 Trigger Source \n
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#0000 : 0

STADC

#0001 : 1

PWM0

#0010 : 2

PWM1

#0011 : 3

PWM2

#0100 : 4

PWM3

#0101 : 5

PWM4

#0110 : 6

PWM5

#0111 : 7

TMR0

#1000 : 8

TMR1

#1001 : 9

TMR2

#1010 : 10

ADC0IF

#1011 : 11

ADC1IF

End of enumeration elements list.

ADC0PWMTRGSEL : PWM Trigger Selection for ADC0\n
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 0

EPWM Signal Falling

#01 : 1

EPWM Counter Central

#10 : 2

EPWM signal Rising

#11 : 3

Period

End of enumeration elements list.

ADC0STADCSEL : ADC0 External Trigger Pin (STADC) Trigger Selection\n
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

#00 : 0

Rising

#01 : 1

Falling

#10 : 2

Rising or Falling

#11 : 3

Reserved

End of enumeration elements list.

ADC1TRGSOR : ADC1 Trigger Source \n
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0000 : 0

STADC

#0001 : 1

PWM0

#0010 : 2

PWM1

#0011 : 3

PWM2

#0100 : 4

PWM3

#0101 : 5

PWM4

#0110 : 6

PWM5

#0111 : 7

TMR0

#1000 : 8

TMR1

#1001 : 9

TMR2

#1010 : 10

ADC0IF

#1011 : 11

ADC1IF

End of enumeration elements list.

ADC1PWMTRGSEL : PWM Trigger Selection for ADC1\n
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

#00 : 0

EPWM Signal Falling

#01 : 1

EPWM Counter Central

#10 : 2

EPWM signal Rising

#11 : 3

Period

End of enumeration elements list.

ADC1STADCSEL : ADC1 External Trigger Pin (STADC) Trigger Selection\n
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

#00 : 0

Rising

#01 : 1

Falling

#10 : 2

Rising or Falling

#11 : 3

Reserved

End of enumeration elements list.


ADC_TRGDLY (TRGDLY)

ADC Trigger Delay Control Register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_TRGDLY ADC_TRGDLY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC0DELAY ADC1DELAY

ADC0DELAY : ADC0 Trigger Delay Timer Setting this field will delay ADC start conversion time after ADCxTRGCTL trigger is coming. (x:0/1) Delay time is (4 * ADC0DELAY) * system clock
bits : 0 - 7 (8 bit)
access : read-write

ADC1DELAY : ADC1 Trigger Delay Timer Setting this field will delay ADC start conversion time after ADCxTRGCTL trigger is coming. (x:0/1) Delay time is (4 * ADC1DELAY) * system clock
bits : 16 - 23 (8 bit)
access : read-write


ADC_SMPCNT (SMPCNT)

ADC Sampling Time Counter Register
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_SMPCNT ADC_SMPCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCSMPCNT

ADCSMPCNT : ADC Sampling Counter\nADC sampling counters are 6 ADC clock is suggestion\n
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0 : 0

1 * ADC Clock

1 : 1

2 * ADC Clock

2 : 2

3 * ADC Clock

3 : 3

4 * ADC Clock

4 : 4

5 * ADC Clock

5 : 5

6 * ADC Clock

6 : 6

7 * ADC Clock

7 : 7

8 * ADC Clock

8 : 8

16 * ADC Clock

9 : 9

32 * ADC Clock

10 : 10

64 * ADC Clock

11 : 11

128 * ADC Clock

12 : 12

256 * ADC Clock

13 : 13

512 * ADC Clock

14 : 14

1024 * ADC Clock

15 : 15

1024 * ADC Clock

End of enumeration elements list.


ADC_STATUS (STATUS)

ADC Status Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_STATUS ADC_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC0IF ADC0OV ADC0BUSY ADC0CH ADC1IF ADC1OV ADC1BUSY ADC1CH WCMPIF LOWFG MIDFG HIGHFG

ADC0IF : A/D Conversion End Flag A status flag that indicates the end of A/D conversion. ADF is set to 1 When A/D conversion ends. This flag can be cleared by writing 1 to itself.
bits : 0 - 0 (1 bit)
access : read-write

ADC0OV : Over Run Flag\nIt is a mirror to OV bit in ADDR.
bits : 1 - 1 (1 bit)
access : read-write

ADC0BUSY : BUSY/IDLE\nThis bit is mirror of as ADST bit in ADCR.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

A/D converter is in idle state

#1 : 1

A/D converter is busy at conversion

End of enumeration elements list.

ADC0CH : Current Conversion Channel\nIt is read only.
bits : 4 - 7 (4 bit)
access : read-write

ADC1IF : ADC1 Conversion End Flag A status flag that indicates the end of A/D conversion. ADF is set to 1 When A/D conversion ends. This flag can be cleared by writing 1 to itself.
bits : 8 - 8 (1 bit)
access : read-write

ADC1OV : Over Run Flag\nIt is a mirror to OV bit in ADDR.
bits : 9 - 9 (1 bit)
access : read-write

ADC1BUSY : BUSY/IDLE\nThis bit is mirror of as ADST bit in ADCR.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

A/D converter is in idle state

#1 : 1

A/D converter is busy at conversion

End of enumeration elements list.

ADC1CH : Current Conversion Channel\nIt is read only.
bits : 12 - 15 (4 bit)
access : read-write

WCMPIF : Window Comparator Interrupt Flag When Windows Comparator has generat a result output, this bit is set to 1 . Then it is cleared by writing 1 to ifself.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Conversion result in ADC_DAT1 does not meets the WCMPLOWDAT setting

#1 : 1

Conversion result in ADC_DAT1 meets the WCMPLOWDAT setting

End of enumeration elements list.

LOWFG : Window Comparator Low Bound Flag When A/D conversion result lower than the setting condition in Low Bound (WCMPLOWDAT), this bit is set to 1 . Then it is cleared by writing 1 to ifself.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

Conversion result in ADC_DAT1 does not meet the WCMPLOWDAT setting

#1 : 1

Conversion result in ADC_DAT1 meets the WCMPLOWDAT setting

End of enumeration elements list.

MIDFG : Window Comparator Middle Bound Flag When A/D conversion result is between High Bound (WCMPHIGHDAT) and Low Bound (WCMPLOWDAT), this bit is set to 1 . Then it is cleared by writing 1 to ifself.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

Conversion result in ADC_DAT1 isn't between High Bound (WCMPHIGHDAT) and Low Bound (WCMPLOWDAT)

#1 : 1

Conversion result in ADC_DAT1 is between High Bound (WCMPHIGHDAT) and Low Bound (WCMPLOWDAT)

End of enumeration elements list.

HIGHFG : Window Comparator High Bound Flag When A/D conversion result higher than the setting condition in High Bound (WCMPHIGHDAT), this bit is set to 1 . Then it is cleared by writing 1 to ifself.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

Conversion result in ADC_DAT1 does not meet the WCMPHIGHDAT setting

#1 : 1

Conversion result in ADC_DAT1 meets the WCMPHIGHDAT setting

End of enumeration elements list.


ADC_WCMPCTL (WCMPCTL)

ADC Window Comparator Control Register
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_WCMPCTL ADC_WCMPCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WCMPEN WCMPIEN WCMPLOWEN WCMPMIDEN WCMPHIGHEN WFLAGCTL WCMPMCNT

WCMPEN : Window Comparator Enable Control\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Window Comparator Disabled

#1 : 1

Window Comparator Enabled

End of enumeration elements list.

WCMPIEN : Window Comparator Interrupt Enable Control\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Window Comparator Interrupt Disabled

#1 : 1

Window Comparator Interrupt Enabled

End of enumeration elements list.

WCMPLOWEN : Window Comparator Low Flag Enable Control\nset A/D conversion result lower than compare condition Low bound range\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Window Comparator Low Flag Disabled

#1 : 1

Window Comparator Low Flag Enabled

End of enumeration elements list.

WCMPMIDEN : Window Comparator Middle Flag Enable Control\nset A/D conversion result equal to compare condition at Low and High bound range\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Window Comparator Middle Flag Disabled

#1 : 1

Window Comparator Middle Flag Enabled

End of enumeration elements list.

WCMPHIGHEN : Window Comparator High Flag Enable Control\nset A/D conversion result higher than compare condition High bound range\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Window Comparator High Flag Disabled

#1 : 1

Window Comparator High Flag Enabled

End of enumeration elements list.

WFLAGCTL : Window Comparator Flag Control\nWhen the A/D conversion result matches the compare condition\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Auto-update

#1 : 1

none

End of enumeration elements list.

WCMPMCNT : Window Compare Match Count\nWhen the A/D conversion result matches the compare condition\n defined by CMP Flag setting (CMPUPEN, CMPEQUEN, CMPLOWEN and WCFLAGCTL), the internal match counter will increase 1. \nWhen the internal counter reaches the value to (WCMPMCNT ), the CMPIF bit will be set.\n
bits : 8 - 11 (4 bit)
access : read-write


ADC_WCMPDAT (WCMPDAT)

ADC Window Comparator Data Register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_WCMPDAT ADC_WCMPDAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WCMPLOWDAT WCMPHIGHDAT

WCMPLOWDAT : Window Comparator Low Bound Data
bits : 0 - 11 (12 bit)
access : read-write

WCMPHIGHDAT : Window Comparator High Bound Data
bits : 16 - 27 (12 bit)
access : read-write


ADC_DAT1 (DAT1)

ADC Data Register 1
address_offset : 0x4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ADC_DAT1 ADC_DAT1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC0DAT1 ADC0OV ADC0VALID ADC1DAT1 ADC1OV ADC1VALID

ADC0DAT1 : ADC0 Conversion Result for FIFO1\nThis field contains conversion result of ADC.
bits : 0 - 11 (12 bit)
access : read-only

ADC0OV : ADC0Over Run Flag Note1: If converted data in ADC0DAT1[11:0] has not been read before the new conversion result is loaded to this register, OV is set to 1 . Note2: It is cleared by hardware after the ADC_DAT1 register is read.
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

#0 : 0

Data in ADC0DAT1[11:0] is recent conversion result

#1 : 1

Data in ADC0DAT1[11:0]] overwritten

End of enumeration elements list.

ADC0VALID : ADC0 Valid Flag Note: This bit is set to 1 when A/D conversion is completed and cleared by hardware after the ADC_DAT1 register is read.
bits : 15 - 15 (1 bit)
access : read-only

Enumeration:

#0 : 0

Data in ADC0DAT1[11:0] bits not valid

#1 : 1

Data in ADC0DAT1[11:0] bits valid

End of enumeration elements list.

ADC1DAT1 : ADC1 Conversion Result for FIFO1\nThis field contains conversion result of ADC.
bits : 16 - 27 (12 bit)
access : read-only

ADC1OV : ADC1 over Run Flag Note1: If converted data in ADC1DAT1[27:16] has not been read before the new conversion result is loaded to this register, OV is set to 1 . Note2: It is cleared by hardware after the ADC_DAT1 register is read.
bits : 30 - 30 (1 bit)
access : read-only

Enumeration:

#0 : 0

Data in ADC1DAT1[27:16] is recent conversion result

#1 : 1

Data in ADC1DAT1[27:16] overwritten

End of enumeration elements list.

ADC1VALID : ADC1 Valid Flag Note: This bit is set to 1 when A/D conversion is completed and cleared by hardware after the ADC_DAT1 register is read.
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

#0 : 0

Data in ADC1DAT1[27:16] bits not valid

#1 : 1

Data in ADC1DAT1[27:16] bits valid

End of enumeration elements list.



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.