\n
address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
Analog Comparator0 Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACMPEN : Comparator Enable Control\nNote: Comparator output needs to wait 2 us stable time after ACMPEN is set.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Comparator Disabled
#1 : 1
Comparator Enabled
End of enumeration elements list.
ACMPIE : Comparator Interrupt Enable Control
Note1: Interrupt is generated if ACMPIE bit is set to 1 after ACMP conversion is finished.
Note2: ACMP interrupt will wake CPU up in Power-down mode.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
ACMP interrupt function Disabled
#1 : 1
ACMP interrupt function Enabled
End of enumeration elements list.
ACMPHYSEN : Comparator0 Hysteresis Enable Control (Only 20mV)\n
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
ACMP0 Hysteresis function Disabled (Default)
#01 : 1
ACMP0 Hysteresis function at comparator 0 Enabled that the typical range is 10mV
#10 : 2
ACMP0 Hysteresis function at comparator 0 Enabled that the typical range is 90mV
#11 : 3
ACMP0 Hysteresis function Disabled
End of enumeration elements list.
EDGESEL : Interrupt Flag Trigger Edge Detection\n
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Interrupt Flag Trigger Edge Disabled
#01 : 1
Rising
#10 : 2
Falling
#11 : 3
Rising/Falling
End of enumeration elements list.
PBRKSEL : ACMP to EPWM Brake Selection\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
ACMP Result direct output
#1 : 1
ACMP Delay Trigger Result output
End of enumeration elements list.
DLYTRGSEL : Analog Comparator Delay Trigger Mode Trigger Level Selection\n
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Analog Comparator Delay Trigger Mode Trigger Disabled
#01 : 1
Rising
#10 : 2
Falling
#11 : 3
Rising/Falling
End of enumeration elements list.
DLYTRGSOR : Analog Comparator Delay Trigger Mode Trigger Source Selection\n
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 0
PWM0
#01 : 1
PWM2
#10 : 2
PWM4
#11 : 3
Reserved
End of enumeration elements list.
DLYTRGEN : Analog Comparator Delay Trigger Mode Enable Control\n
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Analog Comparator Delay Trigger Mode Disabled
#1 : 1
Analog Comparator Delay Trigger Mode Enabled
End of enumeration elements list.
DLYTRGIE : Analog Comparator Delay Trigger Mode Interrupt Enable Control\n
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Analog Comparator Delay Trigger Mode Interrupt Disabled
#1 : 1
Analog Comparator Delay Trigger Mode Interrupt Enabled
End of enumeration elements list.
POLARITY : Analog Comparator Polarity Control\n
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Analog Comparator normal output
#1 : 1
Analog Comparator invert output
End of enumeration elements list.
NFCLKS : Noise Filter Clock Pre-divided Selection\nTo determine the sampling frequency of the Noise Filter clock\n
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 0
PCLK
#01 : 1
PCLK / 2
#10 : 2
PCLK / 4
#11 : 3
PCLK / 16
End of enumeration elements list.
NFDIS : Disable Comparator Noise Filter\n
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Noise filter Enabled
#1 : 1
Noise filter Disabled
End of enumeration elements list.
CPNSEL : Comparator Negative Input Select\n
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
ACMP0_N (PB.4)
#01 : 1
Band_Gap
#10 : 2
CRV
#11 : 3
Reserved
End of enumeration elements list.
CPPSEL : Comparator Positive Input Select\n
bits : 28 - 30 (3 bit)
access : read-write
Enumeration:
#000 : 0
ACMP0_P0 (PB.0)
#001 : 1
ACMP0_P1 (PB.1)
#010 : 2
ACMP0_P2 (PB.2)
#011 : 3
ACMP0_P3 (PC.1)
#100 : 4
PGA_CMP
End of enumeration elements list.
PRESET : Comparator Result Preset Value\n
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
0 for preset value
#1 : 1
1 for preset value
End of enumeration elements list.
Analog Comparator Delay Trigger Mode Dleay Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DELAY : Analog Comparator Delay Trigger Mode Dleay cycle
bits : 0 - 8 (9 bit)
access : read-write
Analog Comparator1 Control Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACMPEN : Comparator Enable Control\nNote: Comparator output needs to wait 2 us stable time after ACMPEN is set.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Comparator Disabled
#1 : 1
Comparator Enabled
End of enumeration elements list.
ACMPIE : Comparator Interrupt Enable Control
Note1: Interrupt is generated if ACMPIE bit is set to 1 after ACMP conversion is finished.
Note2: ACMP interrupt will wake CPU up in Power-down mode.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
ACMP interrupt function Disabled
#1 : 1
ACMP interrupt function Enabled
End of enumeration elements list.
ACMPHYSEN : Comparator1 Hysteresis Enable Control (Only 20mV)\n
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
ACMP0 Hysteresis function Disabled (Default)
#01 : 1
ACMP0 Hysteresis function at comparator 0 Enabled that the typical range is 10mV
#10 : 2
ACMP0 Hysteresis function at comparator 0 Enabled that the typical range is 90mV
#11 : 3
ACMP0 Hysteresis function Disabled
End of enumeration elements list.
EDGESEL : Interrupt Flag Trigger Edge Detection\n
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Interrupt Flag Trigger Edge Detection Disable
#01 : 1
Rising
#10 : 2
Falling
#11 : 3
Rising/Falling
End of enumeration elements list.
PBRKSEL : ACMP to EPWM Brake Selection\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
ACMP Result direct output
#1 : 1
ACMP Delay Trigger Result output
End of enumeration elements list.
DLYTRGSEL : Analog Comparator Delay Trigger Mode Trigger Level Selection\n
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Analog Comparator Delay Trigger Mode Trigger Disabled
#01 : 1
Rising
#10 : 2
Falling
#11 : 3
Rising/Falling
End of enumeration elements list.
DLYTRGSOR : Analog Comparator Delay Trigger Mode Trigger Source Selection\n
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 0
PWM0
#01 : 1
PWM2
#10 : 2
PWM4
#11 : 3
Reserved
End of enumeration elements list.
DLYTRGEN : Analog Comparator Delay Trigger Mode Enable\n
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Analog Comparator Delay Trigger Mode Disabled
#1 : 1
Analog Comparator Delay Trigger Mode Enabled
End of enumeration elements list.
DLYTRGIE : Analog Comparator Delay Trigger Mode Interrupt Enable\n
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Analog Comparator Delay Trigger Mode Interrupt Disabled
#1 : 1
Analog Comparator Delay Trigger Mode Interrupt Enabled
End of enumeration elements list.
POLARITY : Analog Comparator Polarity Control\n
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Analog Comparator normal output
#1 : 1
Analog Comparator invert output
End of enumeration elements list.
NFCLKS : Noise Filter Clock Pre-divided Selection\nTo determine the sampling frequency of the Noise Filter clock\n
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 0
PCLK
#01 : 1
PCLK / 2
#10 : 2
PCLK / 4
#11 : 3
PCLK / 16
End of enumeration elements list.
NFDIS : Disable Comparator Noise Filter\n
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Noise filter Enable
#1 : 1
Noise filter Disable
End of enumeration elements list.
CPNSEL : Comparator Negative Input Selection\n
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
ACMP1_N (PB.3)
#01 : 1
Band_Gap
#10 : 2
CRV
#11 : 3
Reserved
End of enumeration elements list.
CPPSEL : Comparator Positive Input Selection\n
bits : 28 - 30 (3 bit)
access : read-write
Enumeration:
#000 : 0
ACMP1_P0 (PC.0)
#001 : 1
ACMP1_P1 (PC.1)
#010 : 2
ACMP1_P2 (PD.1)
#011 : 3
PGA_CMP
End of enumeration elements list.
PRESET : Comparator Result Preset Value\n
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
0 for preset value
#1 : 1
1 for preset value
End of enumeration elements list.
Analog Comparator Status Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACMPF0 : Comparator0 Flag
This bit is set by hardware whenever the comparator0 output changes state. This will cause an interrupt if ACMPIE set.
Write 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write
ACMPF1 : Comparator1 Flag
This bit is set by hardware whenever the comparator1 output changes state. This will cause an interrupt if ACMPIE set.
Write 1 to clear this bit to 0.
bits : 1 - 1 (1 bit)
access : read-write
ACMPO0 : Comparator0 Output\n
bits : 2 - 2 (1 bit)
access : read-write
ACMPO1 : Comparator1 Output\n
bits : 3 - 3 (1 bit)
access : read-write
DLYTRGF0 : Comparator0 Flag
This bit is set by hardware whenever the comparator0 output changes state. This will cause an interrupt if DLYTRGIEN set.
Write 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write
DLYTRGF1 : Comparator1 Flag
This bit is set by hardware whenever the comparator1 output changes state. This will cause an interrupt if DLYTRGIEN set.
Write 1 to clear this bit to 0.
bits : 5 - 5 (1 bit)
access : read-write
DLYTRGO0 : Analog Comparator0 Delay Trigger Mode Comparator Output\n
bits : 6 - 6 (1 bit)
access : read-write
DLYTRGO1 : Analog Comparator1 Delay Trigger Mode Comparator Output\n
bits : 7 - 7 (1 bit)
access : read-write
Analog Comparator Reference Voltage Control Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRVCTL : Comparator Reference Voltage Setting\n
bits : 0 - 3 (4 bit)
access : read-write
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