\n

PGA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PGA_CTL (CTL)


PGA_CTL (CTL)

Programmable Gain Amplifier Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PGA_CTL PGA_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PGAEN GAIN

PGAEN : Programmable Gain Amplifier Enable Control\nNote: The PGA output needs to wait stable 20 s after PGAEN is first set.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Programmable Gain Amplifier Disabled

#1 : 1

Programmable Gain Amplifier Enabled

End of enumeration elements list.

GAIN : PGA Gain Selection\n
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

#000 : 0

2

#001 : 1

3

#010 : 2

5

#011 : 3

7

#100 : 4

9

#101 : 5

11

#110 : 6

13

#111 : 7

1 . (*See Note)

End of enumeration elements list.



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