\n
address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x24 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
System Power-down Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XTLEN : External HXT Or LXT Crystal Oscillator Enable Control (Write Protect)
The default clock source is from HIRC. These two bits are default set to 00 and the XTAL1 and XTAL2 pins are GPIO.
Note: To enable external XTAL function, P5_ALT[1:0] and P5_MFP[1:0] bits must also be set in P5_MFP.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
XTAL1 and XTAL2 are GPIO, disable both LXT HXT (default)
#01 : 1
HXT Enabled
#10 : 2
LXT Enabled
#11 : 3
XTAL1 is external clock input pin, XTAL2 is GPIO
End of enumeration elements list.
HIRCEN : 44.2368 MHz Internal High Speed RC Oscillator (HIRC) Enable Control (Write Protect)\nNote: The default of HIRCEN bit is 1.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
44.2368 MHz internal high speed RC oscillator (HIRC) Disabled
#1 : 1
44.2368 MHz internal high speed RC oscillator (HIRC) Enabled
End of enumeration elements list.
LIRCEN : 10 KHz Internal Low Speed RC Oscillator (LIRC) Enable Control (Write Protest)\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
10 kHz internal low speed RC oscillator (LIRC) Disabled
#1 : 1
10 kHz internal low speed RC oscillator (LIRC) Enabled
End of enumeration elements list.
PDWKDLY : Wake-Up Delay Counter Enable Control (Write Protect)\nWhen the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip work at 4~24 MHz external high speed crystal (HXT), 4096 clock cycles for 32.768 kHz external low speed crystal (LXT), and 16 clock cycles when chip works at 22.1184 MHz internal high speed RC oscillator (HIRC).\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock cycles delay Disabled
#1 : 1
Clock cycles delay Enabled
End of enumeration elements list.
PDWKIEN : Power-Down Mode Wake-Up Interrupt Enable Control (Write Protect)\nNote: The interrupt will occur when both PDWKIF and PDWKIEN are high.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PDWKIF : Power-Down Mode Wake-Up Interrupt Status
Set by Power-down wake-up event , which indicates that resume from Power-down mode
The flag is set if the GPIO, UART, WDT, ACMP, Timer or BOD wake-up occurred.
Note: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1. Write 1 to clear the bit to 0.
bits : 6 - 6 (1 bit)
access : read-write
PDEN : System Power-Down Enable Bit (Write Protect)\nWhen chip wakes up from Power-down mode, this bit is cleared by hardware. User needs to set this bit again for next Power-down.\nIn Power-down mode, 4~24 MHz external high speed crystal oscillator (HXT), 32.768 kHz external low speed crystal oscillator (LXT), and the 22.1184 MHz internal high speed oscillator (HIRC) will be disabled in this mode, and 10 kHz internal low speed RC oscillator (LIRC) are not controlled by Power-down mode.\nIn Power-down mode, the system clock is disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from 10 kHz internal low speed oscillator.\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Chip operating normally or chip in Idle mode because of WFI command
#1 : 1
Chip enters Power-down mode instantly or waits CPU sleep command WFI
End of enumeration elements list.
PDLXT : Enable LXT In Power-Down Mode\nThis bit controls the crystal oscillator active or not in Power-down mode.\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect to Power-down mode
#1 : 1
If XTLEN[1:0] = 10, LXT is still active in Power-down mode
End of enumeration elements list.
HXTGAIN : HXT Gain Selection\n
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 0
Full gain for the frequency up to 24MHz
#01 : 1
3/4 gain for the frequency up to 16MHz
#10 : 2
1/2 gain for the frequency up to 12MHz
#11 : 3
1/4 gain for the frequency up to 4MHz
End of enumeration elements list.
Clock Source Select Control Register 0
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCLKSEL : HCLK Clock Source Selection (Write Protect)\nNote1: Before clock switching, the related clock sources (both pre-select and new-select) must be turn-on and stable.\nNote2: These bits are protected bit, and programming them needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address SYS_BA + 0x100.\nNote3: To set CLK_PWRCTL[1:0] to select HXT or LXT crystal clock.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source is from HXT or LXT
#001 : 1
Reserved
#010 : 2
Reserved
#011 : 3
Clock source is from LIRC
#111 : 7
Clock source is from HIRC
End of enumeration elements list.
STCLKSEL : Cortex-M0 SysTick Clock Source Selection From Reference Clock (Write Protect)\nNote3: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock.
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source is from HXT or LXT
#001 : 1
Reserved
#010 : 2
Clock source is from HXT/2 or LXT/2
#011 : 3
Clock source is from HCLK/2
#111 : 7
Clock source is from HIRC /2
End of enumeration elements list.
Clock Source Select Control Register 1
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDTSEL : WDT CLK Clock Source Selection (Write Protect)\nNote1: These bits are the protected bit, and programming them needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address SYS_BA + 0x100.\nNote2: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source is from HXT or LXT
#01 : 1
Reserved
#10 : 2
Clock source is from HCLK/2048 clock
#11 : 3
Clock source is from LIRC
End of enumeration elements list.
ADCSEL : ADC Peripheral Clock Source Selection\nNote: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source is from HXT or LXT
#01 : 1
Reserved
#10 : 2
Clock source is from HCLK
#11 : 3
Clock source is from HIRC
End of enumeration elements list.
SPISEL : SPI Clock Source Selection\nNote: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock source is from HXT or LXT
#1 : 1
Clock source is from HCLK
End of enumeration elements list.
TMR0SEL : TIMER0 Clock Source Selection\nNote: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock.
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source is from HXT or LXT
#001 : 1
Clock source is from LIRC
#010 : 2
Clock source is from HCLK
#011 : 3
Clock source is from external trigger
#111 : 7
Clock source is from HIRC
End of enumeration elements list.
TMR1SEL : TIMER1 Clock Source Selection\nNote: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock.
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source is from HXT or LXT
#001 : 1
Clock source is from LIRC
#010 : 2
Clock source is from HCLK
#011 : 3
Clock source is from external trigger
#111 : 7
Clock source is from HIRC
End of enumeration elements list.
UART0SEL : UART0 Clock Source Selection\nNote: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source is from HXT or LXT
#01 : 1
Reserved
#10 : 2
Clock source is from HIRC
#11 : 3
Clock source is from HIRC
End of enumeration elements list.
UART1SEL : UART1 Clock Source Selection\nNote: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock.
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from HXT or LXT crystal clock
#01 : 1
Reserved
#10 : 2
Clock source from HIRC oscillator clock
#11 : 3
Reserved
End of enumeration elements list.
Clock Divider Number Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCLKDIV : HCLK Clock Divide Number From HCLK Clock Source\n
bits : 0 - 3 (4 bit)
access : read-write
UART0DIV : UART0 Clock Divide Number From UART0 Clock Source\n
bits : 8 - 11 (4 bit)
access : read-write
UART1DIV : UART1 Clock Divide Number From UART1 Clock Source\n
bits : 12 - 15 (4 bit)
access : read-write
ADCDIV : ADC Peripheral Clock Divide Number From ADC Peripheral Clock Source\n
bits : 16 - 23 (8 bit)
access : read-write
Clock Source Select Control Register 2
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FDIVSEL : Clock Divider Clock Source Selection\nNote: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source is from HXT or LXT
#01 : 1
Reserved
#10 : 2
Clock source is from HCLK
#11 : 3
Clock source is from HIRC
End of enumeration elements list.
Frequency Divider Control Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FSEL : Divider Output Frequency Selection\nThe formula of output frequency is\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FSEL[3:0].
bits : 0 - 3 (4 bit)
access : read-write
CLKOEN : Frequency Divider Enable Control\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Frequency Divider Disabled
#1 : 1
Frequency Divider Enabled
End of enumeration elements list.
DIV1EN : Frequency Divider 1 Enable Control\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Divider output frequency is depended on FSEL value
#1 : 1
Divider output frequency is the same as input clock frequency
End of enumeration elements list.
AHB Devices Clock Enable Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPCKEN : Flash ISP Controller Clock Enable Control\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flash ISP peripheral clock Disabled
#1 : 1
Flash ISP peripheral clock Enabled
End of enumeration elements list.
HDIVEN : Divider Clock Enable Control\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Divider clock Disabled
#1 : 1
Divider clock Enabled
End of enumeration elements list.
APB Devices Clock Enable Control Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDTCKEN : Watchdog Timer Clock Enable Control (Write Protect)\nNote: This bit is the protected bit, and programming it needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address SYS_BA + 0x100.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Watchdog Timer clock Disabled
#1 : 1
Watchdog Timer clock Enabled
End of enumeration elements list.
TMR0CKEN : Timer0 Clock Enable Control\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer0 clock Disabled
#1 : 1
Timer0 clock Enabled
End of enumeration elements list.
TMR1CKEN : Timer1 Clock Enable Control\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer1 clock Disabled
#1 : 1
Timer1 clock Enabled
End of enumeration elements list.
CLKOCKEN : Frequency Divider Output Clock Enable Control\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
FDIV clock Disabled
#1 : 1
FDIV clock Enabled
End of enumeration elements list.
I2CCKEN : I2C Clock Enable Control\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C clock Disabled
#1 : 1
I2C clock Enabled
End of enumeration elements list.
SPICKEN : SPI Peripheral Clock Enable Control\n
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI peripheral clock Disabled
#1 : 1
SPI peripheral clock Enabled
End of enumeration elements list.
UART0CKEN : UART0 Clock Enable Control\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART0 clock Disabled
#1 : 1
UART0 clock Enabled
End of enumeration elements list.
UART1CKEN : UART1 Clock Enable Control\n
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART1 clock Disabled
#1 : 1
UART1 clock Enabled
End of enumeration elements list.
PWMCH01CKEN : PWM_01 Clock Enable Control\n
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM01 clock Disabled
#1 : 1
PWM01 clock Enabled
End of enumeration elements list.
PWMCH23CKEN : PWM_23 Clock Enable Control\n
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM23 clock Disabled
#1 : 1
PWM23 clock Enabled
End of enumeration elements list.
PWMCH45CKEN : PWM_45 Clock Enable Control\n
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM45 clock Disabled
#1 : 1
PWM45 clock Enabled
End of enumeration elements list.
ADCCKEN : Analog-Digital-Converter (ADC) Clock Enable Control\n
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
ADC peripheral clock Disabled
#1 : 1
ADC peripheral clock Enabled
End of enumeration elements list.
ACMPCKEN : Analog Comparator Clock Enable Control\n
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Analog Comparator clock Disabled
#1 : 1
Analog Comparator clock Enabled
End of enumeration elements list.
Clock Status Monitor Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XTLSTB : HXT Or LXT Clock Source Stable Flag
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
HXT or LXT clock is not stable or disabled
#1 : 1
HXT or LXT clock is stable
End of enumeration elements list.
LIRCSTB : LIRC Clock Source Stable Flag (Read Only)\n
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
LIRC clock is not stable or disabled
#1 : 1
LIRC clock is stable
End of enumeration elements list.
HIRCSTB : HIRC Clock Source Stable Flag (Read Only)\n
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
HIRC clock is not stable or disabled
#1 : 1
HIRC clock is stable
End of enumeration elements list.
CLKSFAIL : Clock Switch Fail Flag\nNote1: This bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1.\nNote2: This bit is read only. After selected clock source is stable, hardware will switch system clock to selected clock automatically, and CLKSFAIL will be cleared automatically by hardware.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock switching success
#1 : 1
Clock switching failed
End of enumeration elements list.
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