PDID

REGWRPROT

BODCR

TEMPCR

PORCR

P0_MFP

P1_MFP

P2_MFP

P3_MFP

RSTSRC

P4_MFP

IPRSTC1

IPRSTC2

PDID : Part Device Identification Number\nThis register reflects the device part number code. Software can read this register to identify which device is used. For example, M052LBN PDID code is 0x1000_5200.
bits : 0 - 31 (32 bit)
access : read-only

REGPROTDIS : Register Write-Protection Disable index (Read Only)\n
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

REGWRPROT : Register Write-Protection Code (Write Only) Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value 59h , 16h , 88h to this field. After this sequence is completed, the REGPROTDIS bit will be set to 1 and write-protection registers can be normal write.
bits : 0 - 7 (8 bit)
access : write-only

BOD_EN : Brown-out Detector Enable Control (Write Protect) The default value is set by flash controller user configuration register config0 bit[23] Note: This bit is the protected bit, and programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOD_VL : Brown-out Detector Threshold Voltage Select (Write Protect)\n
bits : 1 - 2 (2 bit)
access : read-write

BOD_RSTEN : Brown-out Reset Enable Control (Write Protect) Note1: While the Brown-out Detector function is enabled (BOD_EN high) and BOD reset function is enabled (BOD_RSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BOD_OUT high). Note2: The default value is set by flash controller user configuration register config0 bit[20]. Note3: This bit is the protected bit, and programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOD_INTF : Brown-out Detector Interrupt Flag\nNote: Write 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOD_LPM : Brown-out Detector Low power Mode (Write Protect) Note1: The BOD consumes about 100 uA in Normal mode, and the low power mode can reduce the current to about 1/10 but slow the BOD response. Note2: This bit is the protected bit, and programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOD_OUT : Brown-out Detector Output Status\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVR_EN : Low Voltage Reset Enable Control (Write Protect) The LVR function reset the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default. Note: This bit is the protected bit, and programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VTEMP_EN : Temperature Sensor Enable Control\nThis bit is used to enable/disable temperature sensor function.\nNote: After this bit is set to 1, the value of temperature sensor output can be obtained from the ADC conversion result. Please refer to the ADC chapter for detailed ADC conversion functional description.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

POR_DIS_CODE : Power-on Reset Enable Control (Write Protect) When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field. The POR function will be active again when this field is set to another value or chip is reset by other reset source, including: nRST, Watchdog reset, LVR reset, BOD reset, ICE reset command and the software-chip reset function. Note: This bit is the protected bit, and programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 0 - 15 (16 bit)
access : read-write

P0_MFP : P0 Multiple Function Selection\nThe pin function of P0 depends on P0_MFP and P0_ALT.\nRefer to P0_ALT for detailed description.
bits : 0 - 7 (8 bit)
access : read-write

P0_ALT0 : P0.0 Alternate Function Selection\n
bits : 8 - 8 (1 bit)
access : read-write

P0_ALT1 : P0.1 Alternate Function Selection\n
bits : 9 - 9 (1 bit)
access : read-write

P0_ALT2 : P0.2 Alternate Function Selection\n
bits : 10 - 10 (1 bit)
access : read-write

P0_ALT3 : P0.3 Alternate Function Selection\n
bits : 11 - 11 (1 bit)
access : read-write

P0_ALT4 : P0.4 Alternate Function Selection\n
bits : 12 - 12 (1 bit)
access : read-write

P0_ALT5 : P0.5 Alternate Function Selection\n
bits : 13 - 13 (1 bit)
access : read-write

P0_ALT6 : P0.6 Alternate Function Selection\n
bits : 14 - 14 (1 bit)
access : read-write

P0_ALT7 : P0.7 Alternate Function Selection\n
bits : 15 - 15 (1 bit)
access : read-write

P0_TYPEn : P0[7:0] Input Schmitt Trigger Function Enable Control\n
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

P0_ALT10 : P0.0 Alternate Function Selection1 \nThe pin function of P0.0 depends on P0_MFP[0], P0_ALT[0], and P0_ALT1[0].\nRefer to P0_ALT[0] for detailed description.
bits : 24 - 24 (1 bit)
access : read-write

P0_ALT11 : P0.1 Alternate Function Selection1 \nThe pin function of P0.1 depends on P0_MFP[1], P0_ALT[1], and P0_ALT1[1].\nRefer to P0_ALT[1] for detailed description.
bits : 25 - 25 (1 bit)
access : read-write

P1_MFP : P1 Multiple Function Selection\nThe pin function of P1 depends on P1_MFP and P1_ALT.\nRefer to P1_ALT for detailed description.
bits : 0 - 7 (8 bit)
access : read-write

P1_ALT0 : P1.0 Alternate Function Selection\n
bits : 8 - 8 (1 bit)
access : read-write

P1_ALT1 : P1.1 Alternate Function Selection\n
bits : 9 - 9 (1 bit)
access : read-write

P1_ALT2 : P1.2 Alternate Function Selection\n
bits : 10 - 10 (1 bit)
access : read-write

P1_ALT3 : P1.3 Alternate Function Selection\n
bits : 11 - 11 (1 bit)
access : read-write

P1_ALT4 : P1.4 Alternate Function Selection\n
bits : 12 - 12 (1 bit)
access : read-write

P1_ALT5 : P1.5 Alternate Function Selection\n
bits : 13 - 13 (1 bit)
access : read-write

P1_ALT6 : P1.6 Alternate Function Selection\n
bits : 14 - 14 (1 bit)
access : read-write

P1_ALT7 : P1.7 Alternate Function Selection\n
bits : 15 - 15 (1 bit)
access : read-write

P1_TYPEn : P1[7:0] Input Schmitt Trigger function Enable Control\n
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

P2_MFP : P2 Multiple Function Selection\nThe pin function of P2 depends on P2_MFP and P2_ALT.\nRefer to P2_ALT for detailed description.
bits : 0 - 7 (8 bit)
access : read-write

P2_ALT0 : P2.0 Alternate Function Selection\n
bits : 8 - 8 (1 bit)
access : read-write

P2_ALT1 : P2.1 Alternate Function Selection\n
bits : 9 - 9 (1 bit)
access : read-write

P2_ALT2 : P2.2 Alternate Function Selection\n
bits : 10 - 10 (1 bit)
access : read-write

P2_ALT3 : P2.3 Alternate Function Selection\n
bits : 11 - 11 (1 bit)
access : read-write

P2_ALT4 : P2.4 Alternate Function Selection\n
bits : 12 - 12 (1 bit)
access : read-write

P2_ALT5 : P2.5 Alternate Function Selection\n
bits : 13 - 13 (1 bit)
access : read-write

P2_ALT6 : P2.6 Alternate Function Selection\n
bits : 14 - 14 (1 bit)
access : read-write

P2_ALT7 : P2.7 Alternate Function Selection\n
bits : 15 - 15 (1 bit)
access : read-write

P2_TYPEn : P2[7:0] Input Schmitt Trigger Function Enable Control\n
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

P3_MFP : P3 Multiple Function Selection\nThe pin function of P3 depends on P3_MFP and P3_ALT.\nRefer to P3_ALT for detailed description.
bits : 0 - 7 (8 bit)
access : read-write

P3_ALT0 : P3.0 Alternate Function Selection\n
bits : 8 - 8 (1 bit)
access : read-write

P3_ALT1 : P3.1 Alternate Function Selection\n
bits : 9 - 9 (1 bit)
access : read-write

P3_ALT2 : P3.2 Alternate Function Selection\n
bits : 10 - 10 (1 bit)
access : read-write

P3_ALT3 : P3.3 Alternate Function Selection\n
bits : 11 - 11 (1 bit)
access : read-write

P3_ALT4 : P3.4 Alternate Function Selection\n
bits : 12 - 12 (1 bit)
access : read-write

P3_ALT5 : P3.5 Alternate Function Selection\n
bits : 13 - 13 (1 bit)
access : read-write

P3_ALT6 : P3.6 Alternate Function Selection\n
bits : 14 - 14 (1 bit)
access : read-write

P3_ALT7 : P3.7 Alternate Function Selection\n
bits : 15 - 15 (1 bit)
access : read-write

P3_TYPEn : P3[7:0] Input Schmitt Trigger function Enable\n
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTS_POR : Power-on Reset Flag The RSTS_POR flag is set by the reset signal from the Power-on Reset (POR) controller or bit CHIP_RST (IPRSTC1[0]) to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTS_RESET : Reset Pin Reset Flag The RSTS_RESET flag is set by the reset signal from the nRST pin to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTS_WDT : Watchdog Reset Flag The RSTS_WDT flag is set by the reset signal from the watchdog timer to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTS_LVR : Low Voltage Reset Flag The RSTS_LVR flag is set by the reset signal from the Low-Voltage-Reset controller to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTS_BOD : Brown-out Detector Reset Flag The RSTS_BOD flag is set by the reset signal from the Brown-out Detector to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTS_MCU : MCU Reset Flag The RSTS_MCU flag is set by the reset signal from the Cortex-M0 core to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTS_CPU : CPU Reset Flag\nThe RSTS_CPU flag is set by hardware if software writes CPU_RST (IPRSTC1[1]) 1 to reset Cortex-M0 core and Flash memory controller (FMC).\nNote: Write 1 to clear this bit to 0.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

P4_MFP : P4 Multiple Function Selection\nThe pin function of P4 depends on P4_MFP and P4_ALT.\nRefer to P4_ALT for detailed description.
bits : 0 - 7 (8 bit)
access : read-write

P4_ALT0 : P4.0 Alternate Function Selection\n
bits : 8 - 8 (1 bit)
access : read-write

P4_ALT1 : P4.1 Alternate Function Selection\n
bits : 9 - 9 (1 bit)
access : read-write

P4_ALT2 : P4.2 Alternate Function Selection\n
bits : 10 - 10 (1 bit)
access : read-write

P4_ALT3 : P4.3 Alternate Function Selection\n
bits : 11 - 11 (1 bit)
access : read-write

P4_ALT4 : P4.4 Alternate Function Selection\n
bits : 12 - 12 (1 bit)
access : read-write

P4_ALT5 : P4.5 Alternate Function Selection\n
bits : 13 - 13 (1 bit)
access : read-write

P4_ALT6 : P4.6 Alternate Function Selection\n
bits : 14 - 14 (1 bit)
access : read-write

P4_ALT7 : P4.7 Alternate Function Selection\n
bits : 15 - 15 (1 bit)
access : read-write

P4_TYPEn : P4[7:0] Input Schmitt Trigger function Enable Control\n
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHIP_RST : Chip One-shot Reset (Write Protect) Setting this bit will reset the whole chip, including Cortext-M0 core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles. The CHIP_RST is the same as the POR reset. All the chip controllers are reset and the chip setting from CONFIG0 are also reload. Note: This bit is the protected bit, and programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPU_RST : Cortext-M0 Core One-shot Reset (Write Protect) Setting this bit will only reset the Cortext-M0 core and Flash Memory Controller (FMC), and this bit will automatically return 0 after the two clock cycles. Note: This bit is the protected bit, and programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EBI_RST : EBI Controller Reset (Write Protect) Set this bit to 1 will generate a reset signal to the EBI. User needs to set this bit to 0 to release from the reset state. Note: This bit is the protected bit, and programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HDIV_RST : HDIV Controller Reset (Write Protect) Set this bit to 1 will generate a reset signal to the hardware divider. User need to set this bit to 0 to release from the reset state. Note: This bit is the protected bit, and programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPIO_RST : GPIO (P0~P4) Controller Reset\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0_RST : Timer0 Controller Reset\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1_RST : Timer1 Controller Reset\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR2_RST : Timer2 Controller Reset\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR3_RST : Timer3 Controller Reset\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C0_RST : I2C Controller Reset\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C1_RST : I2C1 Controller Reset \n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI0_RST : SPI0 Controller Reset\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI1_RST : SPI1 Controller Reset\n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART0_RST : UART0 Controller Reset\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART1_RST : UART1 Controller Reset\n
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM03_RST : PWM03 Controller Reset\n
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM47_RST : PWM47 Controller Reset\n
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACMP01_RST : Analog Comparator A Controller Reset\n
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACMP23_RST : Analog Comparator B Controller Reset \n
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADC_RST : ADC Controller Reset\n
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.