\n

INT

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x84 byte (0x0)
mem_usage : registers
protection : not protected

Registers

IRQ0_SRC

IRQ4_SRC

IRQ5_SRC

IRQ6_SRC

IRQ7_SRC

IRQ8_SRC

IRQ9_SRC

IRQ10_SRC

IRQ11_SRC

IRQ12_SRC

IRQ13_SRC

IRQ14_SRC

IRQ15_SRC

IRQ1_SRC

IRQ16_SRC

IRQ17_SRC

IRQ18_SRC

IRQ19_SRC

IRQ20_SRC

IRQ21_SRC

IRQ22_SRC

IRQ23_SRC

IRQ24_SRC

IRQ25_SRC

IRQ26_SRC

IRQ27_SRC

IRQ28_SRC

IRQ29_SRC

IRQ30_SRC

IRQ31_SRC

IRQ2_SRC

NMI_SEL

IRQ3_SRC


IRQ0_SRC

IRQ0 (BOD) Interrupt Source Identity
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ0_SRC IRQ0_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_SRC

INT_SRC : IRQ0 Source Identity\nNote: When the interrupt flag is cleared, the corresponding bits will be cleared automatically.
bits : 0 - 2 (3 bit)
access : read-only

Enumeration:

0 : 0

IRQ0 source is not from BOD interrupt (BOD_INT)

1 : 1

IRQ0 source is from BOD interrupt (BOD_INT)

End of enumeration elements list.


IRQ4_SRC

IRQ4 (P0/1) Interrupt Source Identity
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ4_SRC IRQ4_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_SRC

INT_SRC : IRQ4 Source Identity\nNote1: IRQ4 source can be from multiple interrupt sources at the same time.\nNote2: When the interrupt flag is cleared, the corresponding bits will be cleared automatically.
bits : 0 - 2 (3 bit)
access : read-only

Enumeration:

0 : 0

IRQ4 source is not from P1 interrupt (P1_INT).\nIRQ4 source is not from P0 interrupt (P0_INT)

1 : 1

IRQ4 source is from P1 interrupt (P1_INT).\nIRQ4 source is from P0 interrupt (P0_INT)

End of enumeration elements list.


IRQ5_SRC

IRQ5 (P2/3/4) Interrupt Source Identity
address_offset : 0x14 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ5_SRC IRQ5_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_SRC

INT_SRC : IRQ5 Source Identity\nINT_SRC[2]:\nNote1: IRQ5 source can be from multiple interrupt sources at the same time.\nNote2: When the interrupt flag is cleared, the corresponding bits will be cleared automatically.
bits : 0 - 2 (3 bit)
access : read-only

Enumeration:

0 : 0

IRQ5 source is not from P4 interrupt (P4_INT).\nIRQ5 source is not from P3 interrupt (P3_INT).\nIRQ5 source is not from P2 interrupt (P2_INT)

1 : 1

IRQ5 source is from P4 interrupt (P4_INT).\nIRQ5 source is from P3 interrupt (P3_INT).\nIRQ5 source is from P2 interrupt (P2_INT)

End of enumeration elements list.


IRQ6_SRC

IRQ6 (PWMA) Interrupt Source Identity
address_offset : 0x18 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ6_SRC IRQ6_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_SRC

INT_SRC : IRQ6 Source Identity\nINT_SRC[3]:\nNote1: IRQ6 source can be from multiple interrupt sources at the same time.\nNote2: When the interrupt flag is cleared, the corresponding bits will be cleared automatically.
bits : 0 - 3 (4 bit)
access : read-only

Enumeration:

0 : 0

IRQ6 source is not from PWM3(PWMA channel 3) interrupt (PWM3_INT).\nIRQ6 source is not from PWM2(PWMA channel 2) interrupt (PWM2_INT).\nIRQ6 source is not from PWM1(PWMA channel 1) interrupt (PWM1_INT).\nIRQ6 source is not from PWM0(PWMA channel 0) interrupt (PWM0_INT)

1 : 1

IRQ6 source is from PWM3(PWMA channel 3) interrupt (PWM3_INT).\nIRQ6 source is from PWM2(PWMA channel 2) interrupt (PWM2_INT).\nIRQ6 source is from PWM1(PWMA channel 1) interrupt (PWM1_INT).\nIRQ6 source is from PWM0(PWMA channel 0) interrupt (PWM0_INT)

End of enumeration elements list.


IRQ7_SRC

IRQ7 (PWMB) Interrupt Source Identity
address_offset : 0x1C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ7_SRC IRQ7_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_SRC

INT_SRC : IRQ7 Source Identity\nINT_SRC[3]:\nNote1: IRQ7 source can be from multiple interrupt sources at the same time.\nNote2: When the interrupt flag is cleared, the corresponding bits will be cleared automatically.
bits : 0 - 3 (4 bit)
access : read-only

Enumeration:

0 : 0

IRQ7 source is not from PWM7(PWMB channel 3) interrupt (PWM7_INT).\nIRQ7 source is not from PWM6(PWMB channel 2) interrupt (PWM6_INT).\nIRQ7 source is not from PWM5(PWMB channel 1) interrupt (PWM5_INT).\nIRQ7 source is not from PWM4(PWMB channel 0) interrupt (PWM4_INT)

1 : 1

IRQ7 source is from PWM7(PWMB channel 3) interrupt (PWM7_INT).\nIRQ7 source is from PWM6(PWMB channel 2) interrupt (PWM6_INT).\nIRQ7 source is from PWM5(PWMB channel 1) interrupt (PWM5_INT).\nIRQ7 source is from PWM4(PWMB channel 0) interrupt (PWM4_INT)

End of enumeration elements list.


IRQ8_SRC

IRQ8 (TMR0) Interrupt Source Identity
address_offset : 0x20 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ8_SRC IRQ8_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_SRC

INT_SRC : IRQ8 Source Identity\nNote: When the interrupt flag is cleared, the corresponding bits will be cleared automatically.
bits : 0 - 2 (3 bit)
access : read-only

Enumeration:

0 : 0

IRQ8 source is not from Timer0 interrupt (TMR0_INT)

1 : 1

IRQ8 source is from Timer0 interrupt (TMR0_INT)

End of enumeration elements list.


IRQ9_SRC

IRQ9 (TMR1) Interrupt Source Identity
address_offset : 0x24 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ9_SRC IRQ9_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_SRC

INT_SRC : IRQ9 Source Identity\nNote: When the interrupt flag is cleared, the corresponding bits will be cleared automatically.
bits : 0 - 2 (3 bit)
access : read-only

Enumeration:

0 : 0

IRQ9 source is not from Timer1 interrupt (TMR1_INT)

1 : 1

IRQ9 source is from Timer1 interrupt (TMR1_INT)

End of enumeration elements list.


IRQ10_SRC

IRQ10 (TMR2) Interrupt Source Identity
address_offset : 0x28 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ10_SRC IRQ10_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_SRC

INT_SRC : IRQ10 Source Identity\nNote: When the interrupt flag is cleared, the corresponding bits will be cleared automatically.
bits : 0 - 2 (3 bit)
access : read-only

Enumeration:

0 : 0

IRQ10 source is not from Timer2 interrupt (TMR2_INT)

1 : 1

IRQ10 source is from Timer2 interrupt (TMR2_INT)

End of enumeration elements list.


IRQ11_SRC

IRQ11 (TMR3) Interrupt Source Identity
address_offset : 0x2C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ11_SRC IRQ11_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_SRC

INT_SRC : IRQ11 Source Identity\nNote: When the interrupt flag is cleared, the corresponding bits will be cleared automatically.
bits : 0 - 2 (3 bit)
access : read-only

Enumeration:

0 : 0

IRQ11 source is not from Timer3 interrupt (TMR3_INT)

1 : 1

IRQ11 source is from Timer3 interrupt (TMR3_INT)

End of enumeration elements list.


IRQ12_SRC

IRQ12 (UART0) Interrupt Source Identity
address_offset : 0x30 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ12_SRC IRQ12_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_SRC

INT_SRC : IRQ12 Source Identity\nNote: When the interrupt flag is cleared, the corresponding bits will be cleared automatically.
bits : 0 - 2 (3 bit)
access : read-only

Enumeration:

0 : 0

IRQ12 source is not from UART0 interrupt (UART0_INT)

1 : 1

IRQ12 source is from UART0 interrupt (UART0_INT)

End of enumeration elements list.


IRQ13_SRC

IRQ13 (UART1) Interrupt Source Identity
address_offset : 0x34 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ13_SRC IRQ13_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_SRC

INT_SRC : IRQ13 Source Identity\nNote: When the interrupt flag is cleared, the corresponding bits will be cleared automatically.
bits : 0 - 2 (3 bit)
access : read-only

Enumeration:

0 : 0

IRQ13 source is not from UART1 interrupt (UART1_INT)

1 : 1

IRQ13 source is from UART1 interrupt (UART1_INT)

End of enumeration elements list.


IRQ14_SRC

IRQ14 (SPI0) Interrupt Source Identity
address_offset : 0x38 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ14_SRC IRQ14_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_SRC

INT_SRC : IRQ14 Source Identity\nNote: When the interrupt flag is cleared, the corresponding bits will be cleared automatically.
bits : 0 - 2 (3 bit)
access : read-only

Enumeration:

0 : 0

IRQ14 source is not from SPI0 interrupt (SPI0_INT)

1 : 1

IRQ14 source is from SPI0 interrupt (SPI0_INT)

End of enumeration elements list.


IRQ15_SRC

IRQ15 (SPI1) Interrupt Source Identity
address_offset : 0x3C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ15_SRC IRQ15_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_SRC

INT_SRC : IRQ15 Source Identity\nNote: When the interrupt flag is cleared, the corresponding bits will be cleared automatically.
bits : 0 - 2 (3 bit)
access : read-only

Enumeration:

0 : 0

IRQ15 source is not from SPI1 interrupt (SPI1_INT)

1 : 1

IRQ15 source is from SPI1 interrupt (SPI1_INT)

End of enumeration elements list.


IRQ1_SRC

IRQ1 (WDT) Interrupt Source Identity
address_offset : 0x4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ1_SRC IRQ1_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_SRC

INT_SRC : IRQ1 Source Identity\nNote: When the interrupt flag is cleared, the corresponding bits will be cleared automatically.
bits : 0 - 2 (3 bit)
access : read-only

Enumeration:

0 : 0

IRQ1 source is not from watchdog interrupt (WDT _INT)

1 : 1

IRQ1 source is from watchdog interrupt (WDT_INT)

End of enumeration elements list.


IRQ16_SRC

Reserved.
address_offset : 0x40 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ16_SRC IRQ16_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IRQ17_SRC

Reserved.
address_offset : 0x44 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ17_SRC IRQ17_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IRQ18_SRC

IRQ18 (I2C0) Interrupt Source Identity
address_offset : 0x48 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ18_SRC IRQ18_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_SRC

INT_SRC : IRQ18 Source Identity\nNote: When the interrupt flag is cleared, the corresponding bits will be cleared automatically.
bits : 0 - 2 (3 bit)
access : read-only

Enumeration:

0 : 0

IRQ18 source is not from I2C0 interrupt (I2C0_INT)

1 : 1

IRQ18 source is from I2C0 interrupt (I2C0_INT)

End of enumeration elements list.


IRQ19_SRC

IRQ19 (I2C1) Interrupt Source Identity
address_offset : 0x4C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ19_SRC IRQ19_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_SRC

INT_SRC : IRQ19 Source Identity \nNote: When the interrupt flag is cleared, the corresponding bits will be cleared automatically.
bits : 0 - 2 (3 bit)
access : read-only

Enumeration:

0 : 0

IRQ19 source is not from I2C1 interrupt (I2C1_INT)

1 : 1

IRQ19 source is from I2C1 interrupt (I2C1_INT)

End of enumeration elements list.


IRQ20_SRC

Reserved.
address_offset : 0x50 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ20_SRC IRQ20_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IRQ21_SRC

Reserved.
address_offset : 0x54 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ21_SRC IRQ21_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IRQ22_SRC

Reserved.
address_offset : 0x58 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ22_SRC IRQ22_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IRQ23_SRC

Reserved.
address_offset : 0x5C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ23_SRC IRQ23_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IRQ24_SRC

Reserved.
address_offset : 0x60 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ24_SRC IRQ24_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IRQ25_SRC

IRQ25 (ACMP01) Interrupt Source Identity
address_offset : 0x64 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ25_SRC IRQ25_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_SRC

INT_SRC : IRQ25 Source Identity\nNote: When the interrupt flag is cleared, the corresponding bits will be cleared automatically.
bits : 0 - 2 (3 bit)
access : read-only

Enumeration:

0 : 0

IRQ25 source is not from ACMP01 interrupt (ACMP01_INT)

1 : 1

IRQ25 source is from ACMP01 interrupt (ACMP01_INT)

End of enumeration elements list.


IRQ26_SRC

IRQ26 (ACMP23) Interrupt Source Identity
address_offset : 0x68 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ26_SRC IRQ26_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_SRC

INT_SRC : IRQ26 Source Identity \nNote: When the interrupt flag is cleared, the corresponding bits will be cleared automatically.
bits : 0 - 2 (3 bit)
access : read-only

Enumeration:

0 : 0

IRQ26 source is not from ACMP23 interrupt (ACMP23_INT)

1 : 1

IRQ26 source is from ACMP23 interrupt (ACMP23_INT)

End of enumeration elements list.


IRQ27_SRC

Reserved.
address_offset : 0x6C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ27_SRC IRQ27_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IRQ28_SRC

IRQ28 (PWRWU) Interrupt Source Identity
address_offset : 0x70 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ28_SRC IRQ28_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_SRC

INT_SRC : IRQ28 Source Identity\nNote: When the interrupt flag is cleared, the corresponding bits will be cleared automatically.
bits : 0 - 2 (3 bit)
access : read-only

Enumeration:

0 : 0

IRQ28 source is not from Power-down mode Wake-up interrupt (PWRWU_INT)

1 : 1

IRQ28 source is from Power-down mode Wake-up interrupt interrupt (PWRWU_INT)

End of enumeration elements list.


IRQ29_SRC

IRQ29 (ADC) Interrupt Source Identity
address_offset : 0x74 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ29_SRC IRQ29_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_SRC

INT_SRC : IRQ29 Source Identity\nNote: When the interrupt flag is cleared, the corresponding bits will be cleared automatically.
bits : 0 - 2 (3 bit)
access : read-only

Enumeration:

0 : 0

IRQ29 source is not from ADC interrupt (ADC_INT)

1 : 1

IRQ29 source is from ADC interrupt (ADC_INT)

End of enumeration elements list.


IRQ30_SRC

Reserved.
address_offset : 0x78 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ30_SRC IRQ30_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IRQ31_SRC

Reserved.
address_offset : 0x7C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ31_SRC IRQ31_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IRQ2_SRC

IRQ2 (EINT0) Interrupt Source Identity
address_offset : 0x8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ2_SRC IRQ2_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_SRC

INT_SRC : IRQ2 Source Identity\nNote: When the interrupt flag is cleared, the corresponding bits will be cleared automatically.
bits : 0 - 2 (3 bit)
access : read-only

Enumeration:

0 : 0

IRQ2 source is not from external signal interrupt 0 - P3.2 (EINT0)

1 : 1

IRQ2 source is from external signal interrupt 0 - P3.2 (EINT0)

End of enumeration elements list.


NMI_SEL

NMI Source Interrupt Select Control Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NMI_SEL NMI_SEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NMI_SEL NMI_EN

NMI_SEL : NMI Interrupt Source Selection\nThe NMI interrupt to Cortex-M0 can be selected from one of the peripheral interrupt by setting NMI_SEL.
bits : 0 - 4 (5 bit)
access : read-write

NMI_EN : NMI Interrupt Enable Control (Write Protect) Note: This bit is the protected bit and programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

NMI interrupt Disabled

#1 : 1

NMI interrupt Enabled

End of enumeration elements list.


IRQ3_SRC

IRQ3 (EINT1) Interrupt Source Identity
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQ3_SRC IRQ3_SRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_SRC

INT_SRC : IRQ3 Source Identity\nNote: When the interrupt flag is cleared, the corresponding bits will be cleared automatically.
bits : 0 - 2 (3 bit)
access : read-only

Enumeration:

0 : 0

IRQ3 source is not from external signal interrupt 1 - P3.3 (EINT1)

1 : 1

IRQ3 source is from external signal interrupt 1 - P3.3 (EINT1)

End of enumeration elements list.



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