ADDR0

ADDR4

ADDR5

ADDR6

ADDR7

ADCR

ADCHER

ADCMPR0

ADCMPR1

ADSR

ADDR1

ADTDCR

ADDR2

ADDR3

RSLT : A/D Conversion Result\nThis field contains conversion result of ADC.
bits : 0 - 15 (16 bit)
access : read-only

OVERRUN : Overrun Flag (Read Only)\nIf converted data in RSLT has not been read before new conversion result is loaded to this register, OVERRUN is set to 1. It is cleared by hardware after ADDR register is read.
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

VALID : Valid Flag \nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read.\nThis is a read only bit.\nNote: When ADC is converting, if user wants to monitor the VALID flag of a specified channel, user should poll the VALID bit of ADSR register instead of polling this bit (M05xxBN only).
bits : 17 - 17 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ADEN : A/D Converter Enable\nNote: Before starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit to save power consumption.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADIE : A/D Interrupt Enable Control\nA/D conversion end interrupt request is generated if ADIE bit is set to 1.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADMD : A/D Converter Operation Mode Control\nNote1: When changing the operation mode, software should clear ADST bit firstly.\nNote2: In Burst mode, the A/D result data always at Data Register 0.
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRGS : Hardware Trigger Source\nSoftware should clear TRGEN bit and ADST bit to 0 before changing TRGS.\nNote: ADC hardware trigger source does not support PWM trigger (M05xxBN only).
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRGCOND : External Trigger Condition\nThese two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and at least 4 PCLKs for edge trigger.\n
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRGEN : External Trigger Enable Control\nEnable or disable triggering of A/D conversion by external STADC pin. If external trigger is enabled, the ADST bit can be set to 1 by the selected hardware trigger source.\nNote: The ADC external trigger function is only supported in Single-cycle Scan mode.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DIFFEN : Differential Input Mode Control\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADST : A/D Conversion Start\nADST bit can be set to 1 from two sources: software or external pin STADC. ADST will be cleared to 0 by hardware automatically at the ends of Single mode and Single-cycle Scan mode. In Continuous Scan mode and Burst mode, A/D conversion is continuously performed until software writes 0 to this bit or chip is reset.\nNote: After the ADST bit is cleared to 0, user must wait at least one ADC peripheral clock cycle before setting the ADST bit to 1 again (M05xxBN only).
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMOF : Differential Input Mode Output Format\nNote: Burst mode and ADC compare function cannot suppert 2's complement output format, this DMOF bit must be cleared to 0 (M05xxBN only).
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN : Analog Input Channel Enable Control\nSet CHEN[7:0] to enable the corresponding analog input channel 7 ~ 0. If DIFFEN bit is set to 1, only the even number channel needs to be enabled.\n
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PRESEL : Analog Input Channel 7 Source Selection\nNote: When the band-gap voltage is selected as the analog input source of ADC channel 7, ADC peripheral clock rate needs to be limited to lower than 300 kHz.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPEN : Compare Enable Control\nSet this bit to 1 to enable ADC controller to compare CMPD[11:0] with specified channel conversion result when converted data is loaded into ADDR register.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPIE : Compare Interrupt Enable Control\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPFx bit will be asserted, in the meanwhile, if CMPIE is set to 1, a compare interrupt request is generated.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPCOND : Compare Condition\nNote: When the internal counter reaches to (CMPMATCNT +1), the CMPFx bit will be set.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPCH : Compare Channel Selection\n
bits : 3 - 5 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPMATCNT : Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2], the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPFx bit will be set.
bits : 8 - 11 (4 bit)
access : read-write

CMPD : Comparison Data\nThe 12-bit data is used to compare with conversion result of specified channel.\nNote: When DIFFEN bit is set to 1, ADC comparator compares CMPD with conversion result with unsigned format (M05xxBN only). CMPD should be filled in unsigned format (straight binary format).
bits : 16 - 27 (12 bit)
access : read-write

ADF : A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion. Software can write 1 to clear this bit.\nADF is set to 1 at the following three conditions:\nWhen A/D conversion ends in Single mode.\nWhen A/D conversion ends on all specified channels in Single-cycle Scan mode and Continuous Scan mode.\nWhen more than 4 samples in FIFO in Burst mode.
bits : 0 - 0 (1 bit)
access : read-write

CMPF0 : Compare Flag 0\nWhen the A/D conversion result of the selected channel meets setting condition in ADCMPR0 then this bit is set to 1. This bit is cleared by writing 1 to it.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPF1 : Compare Flag 1 When the A/D conversion result of the selected channel meets setting condition in ADCMPR1 then this bit is set to 1 it is cleared by writing 1 to self.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUSY : BUSY/IDLE\nThis bit is a mirror of ADST bit in ADCR register. It is read only.\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHANNEL : Current Conversion Channel\nIt is read only.
bits : 4 - 6 (3 bit)
access : read-write

VALID : Data Valid Flag (Read Only)\nIt is a mirror of VALID bit in ADDRx register.\nWhen ADC is in Burst mode and any conversion result is valid, all bits of VALID[7:0] will be set to 1.
bits : 8 - 15 (8 bit)
access : read-only

OVERRUN : Overrun Flag (Read Only)\nIt is a mirror of OVERRUN bit in ADDRx register.\nWhen ADC is in Burst mode and the FIFO is overrun, all bits of OVERRUN[7:0] will be set to 1.
bits : 16 - 23 (8 bit)
access : read-only

PTDT : PWM Trigger Delay Time\nSet this field will delay ADC start conversion time after PWM trigger.\nPWM trigger delay time is (4 * PTDT) * system clock
bits : 0 - 7 (8 bit)
access : read-write