SPI_CNTRL

SPI_RX0

SPI_TX0

SPI_CNTRL2

SPI_DIVIDER

SPI_FIFO_CTL

SPI_STATUS

SPI_SSR

GO_BUSY : SPI Transfer Trigger and Busy Status\nIn FIFO mode, this bit will be controlled by hardware. Software cannot modify this bit.\nIf FIFO mode is disabled, during the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically.\nNote 1: When FIFO mode is disabled, all configurations should be ready before writing 1 to the GO_BUSY bit.\nNote 2: In M05xxDN/DE SPI Slave mode, if FIFO mode is disabled and the SPI bus clock is kept at idle state during a data transfer, the GO_BUSY bit will not be cleared to 0 when slave select signal goes to inactive state.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

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RX_NEG : Receive on Negative Edge\n
bits : 1 - 1 (1 bit)
access : read-write

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TX_NEG : Transmit on Negative Edge\n
bits : 2 - 2 (1 bit)
access : read-write

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TX_BIT_LEN : Transfer Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n
bits : 3 - 7 (5 bit)
access : read-write

LSB : LSB First\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

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CLKP : Clock Polarity\n
bits : 11 - 11 (1 bit)
access : read-write

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SP_CYCLE : Suspend Interval (Master Only)\nThese four bits provide configurable suspend interval between two successive transactions in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word.\nThe default value is 0x3. The period of the suspend interval is obtained according to the following equation:\n(SP_CYCLE[3:0] + 0.5) * period of SPICLK clock cycle\nExample:\n
bits : 12 - 15 (4 bit)
access : read-write

IF : Unit-Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
bits : 16 - 16 (1 bit)
access : read-write

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IE : Unit-Transfer Interrupt Enable Control\n
bits : 17 - 17 (1 bit)
access : read-write

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SLAVE : Slave Mode Control\n
bits : 18 - 18 (1 bit)
access : read-write

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REORDER : Byte Reorder Function and Byte Suspend Function Selection\nNote: Byte reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.
bits : 19 - 19 (1 bit)
access : read-write

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FIFO : FIFO Mode Enable Control \nIn Master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set to 1 automatically after writing data into the 8-depth transmit FIFO. When all data stored at transmit FIFO buffer are transferred, the GO_BUSY bit will back to 0.\nNote 1: Before enabling FIFO mode, the other related settings should be set in advance.\nNote 2: On M05xxBN, this bit must be 0.
bits : 21 - 21 (1 bit)
access : read-write

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RX_EMPTY : Receive FIFO Buffer Empty Indicator (Read Only) \nIt is a mutual mirror bit of SPI_CNTRL[24]. \n
bits : 24 - 24 (1 bit)
access : read-only

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RX_FULL : Receive FIFO Buffer Full Indicator (Read Only) \nIt is a mutual mirror bit of SPI_STATUS[25].\n
bits : 25 - 25 (1 bit)
access : read-only

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TX_EMPTY : Transmit FIFO Buffer Empty Indicator (Read Only) \nIt is a mutual mirror bit of SPI_STATUS[26]. \n
bits : 26 - 26 (1 bit)
access : read-only

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TX_FULL : Transmit FIFO Buffer Full Indicator (Read Only) \nIt is a mutual mirror bit of SPI_STATUS[27]. \n
bits : 27 - 27 (1 bit)
access : read-only

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RX : Data Receive Register\nThe Data Receive Registers hold the value of received data of the last executed transfer. Valid bits depend on the transmit bit length field in the SPI_CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08 and TX_NUM is set to 0x0, bit RX0[7:0] holds the received data. The values of the other bits are unknown. The Data Receive Registers are read-only registers.
bits : 0 - 31 (32 bit)
access : read-only

TX : Data Transmit Register\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. Valid bits depend on the transmit bit length field in the CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08 and the TX_NUM is set to 0x0, the bit TX0[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00 and TX_NUM is set to 0x1, the SPI controller will perform two 32-bit transmit/receive successive using the same setting. The transmission sequence is TX0[31:0] first and then TX1[31:0].
bits : 0 - 31 (32 bit)
access : write-only

NOSLVSEL : Slave 3-wire Mode Enable\nThis is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPICLK, SPI_MISO, and SPI_MOSI when this bit is set to 1.\nNote: In Slave 3-wire mode, the SS_LTRIG bit (SPI_SSR[4]) shall be set as 1.
bits : 8 - 8 (1 bit)
access : read-write

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SLV_ABORT : Slave 3-wire Mode Abort Control\nIn normal operation, there is an interrupt event when the number of received bits meets the requirement which defined in TX_BIT_LEN and TX_NUM. The TX_NUM setting is not available on M05xxDN/DE, and only the setting of TX_BIT_LEN will be considered.\nIf the number of received bits is less than the requirement and there is no more bus clock input over one transfer time in Slave 3-wire mode, user can set this bit to force the current transfer done and then user can get a unit transfer interrupt event. \nNote: This bit will be cleared to 0 automatically by hardware after it is set to 1 by software.
bits : 9 - 9 (1 bit)
access : read-write

SSTA_INTEN : Slave 3-wire Mode Start Interrupt Enable\nIt is used to enable interrupt when the transfer has started in Slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, user can set the SLV_ABORT bit to force the transfer done.\n
bits : 10 - 10 (1 bit)
access : read-write

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SLV_START_INTSTS : Slave 3-wire Mode Start Interrupt Status\nThis bit dedicates if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_STATUS[11].\n
bits : 11 - 11 (1 bit)
access : read-write

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SS_INT_OPT : Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device.\n
bits : 16 - 16 (1 bit)
access : read-write

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BCn : Clock Configuration Backward Compatible Option \nRefer to the description of SPI_DIVIDER register for details.
bits : 31 - 31 (1 bit)
access : read-write

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DIVIDER : Clock Divider\nOnly DIVIDER[7:0] is available. The value in this field is the frequency divider to determine the SPI peripheral clock frequency, fspi, and the SPI master's bus clock frequency on the SPICLK output pin. The frequency is obtained according to the following equation.\nIf the bit of BCn, SPI_CNTRL2[31], is set to 0,\n\nelse if BCn is set to 1,\n\nwhere \n is the SPI peripheral clock source which is defined in the CLKSEL1 register.
bits : 0 - 15 (16 bit)
access : read-write

DIVIDER2 : Clock Divider 2 (M05xxBN Master Mode Only)\nThe value in this field is the 2nd frequency divider for generating the bus clock on the output SPICLK. The desired frequency is obtained according to the following equation:\n\nIf VARCLK_EN is cleared to 0, this setting is unmeaning.
bits : 16 - 31 (16 bit)
access : read-write

RX_CLR : Clear Receive FIFO Buffer\n
bits : 0 - 0 (1 bit)
access : read-write

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TX_CLR : Clear Transmit FIFO Buffer\n
bits : 1 - 1 (1 bit)
access : read-write

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RX_INTEN : Receive Threshold Interrupt Enable Control\n
bits : 2 - 2 (1 bit)
access : read-write

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TX_INTEN : Transmit Threshold Interrupt Enable Control\n
bits : 3 - 3 (1 bit)
access : read-write

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RXOV_INTEN : Receive FIFO Overrun Interrupt Enable Control\n
bits : 6 - 6 (1 bit)
access : read-write

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TIMEOUT_INTEN : Receive FIFO Time-out Interrupt Enable Control\n
bits : 21 - 21 (1 bit)
access : read-write

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RX_THRESHOLD : Received FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting, the RX_INTSTS bit will be set to 1, else the RX_INTSTS bit will be cleared to 0.
bits : 24 - 25 (2 bit)
access : read-write

TX_THRESHOLD : Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting, the TX_INTSTS bit will be set to 1, else the TX_INTSTS bit will be cleared to 0.
bits : 28 - 29 (2 bit)
access : read-write

RX_INTSTS : Receive FIFO Threshold Interrupt Status (Read Only)\n
bits : 0 - 0 (1 bit)
access : read-only

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RX_OVERRUN : Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself.
bits : 2 - 2 (1 bit)
access : read-write

TX_INTSTS : Transmit FIFO Threshold Interrupt Status (Read Only)\n
bits : 4 - 4 (1 bit)
access : read-only

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SLV_START_INTSTS : Slave Start Interrupt Status\nIt is used to dedicate that the transfer has started in Slave 3-wire mode. It's a mutual mirror bit of SPI_CNTRL2[11].\n
bits : 11 - 11 (1 bit)
access : read-write

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RX_FIFO_COUNT : Receive FIFO Data Count (Read Only)\nIndicates the valid data count of receive FIFO buffer.
bits : 12 - 15 (4 bit)
access : read-only

IF : SPI Unit-Transfer Interrupt Flag\nIt is a mutual mirror bit of SPI_CNTRL[16]. \nNote: This bit will be cleared by writing 1 to itself.
bits : 16 - 16 (1 bit)
access : read-write

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TIMEOUT : Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
bits : 20 - 20 (1 bit)
access : read-write

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RX_EMPTY : Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24]. \n
bits : 24 - 24 (1 bit)
access : read-only

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RX_FULL : Receive FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[25]. \n
bits : 25 - 25 (1 bit)
access : read-only

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TX_EMPTY : Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[26]. \n
bits : 26 - 26 (1 bit)
access : read-only

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TX_FULL : Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[27].\n
bits : 27 - 27 (1 bit)
access : read-only

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TX_FIFO_COUNT : Transmit FIFO Data Count (Read Only)\nIndicates the valid data count of transmit FIFO buffer.
bits : 28 - 31 (4 bit)
access : read-only

SSR : Slave Select Control (Master Only)\nIf AUTOSS bit is cleared to 0,\n
bits : 0 - 0 (1 bit)
access : read-write

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SS_LVL : Slave Select Active Level\nThis bit defines the active status of slave select signal (SPISSx).\n
bits : 2 - 2 (1 bit)
access : read-write

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AUTOSS : Automatic Slave Select Function Enable (Master Only)\n
bits : 3 - 3 (1 bit)
access : read-write

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SS_LTRIG : Slave Select Level Trigger Enable (Slave Only)\n
bits : 4 - 4 (1 bit)
access : read-write

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LTRIG_FLAG : Level Trigger Flag\nWhen the SS_LTRIG bit is set in Slave mode, this bit can be read to indicate the received bit number is met the requirement or not.\nNote: This bit is READ only and only available in Slave mode.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.