UA_RBR

UA_THR

UA_MCR

UA_MSR

UA_FSR

UA_ISR

UA_TOR

UA_BAUD

UA_IRCR

UA_ALT_CSR

UA_FUN_SEL

UA_IER

UA_FCR

UA_LCR

RBR : Receive Buffer Register (Read Only)\nBy reading this register, the UART Controller will return an 8-bit data received from UART_RX pin (LSB first).
bits : 0 - 7 (8 bit)
access : read-only

THR : Transmit Holding Register\nBy writing to this register, the UART Controller will send out an 8-bit data through the UART_ TX pin (LSB first).
bits : 0 - 7 (8 bit)
access : write-only

RTS : RTS (Request-To-Send) Signal Control\nThis bit is direct control internal RTS signal active or not, and then drive the RTS pin output with LEV_RTS bit configuration.\nNote1: This RTS signal control bit is not effective when RTS auto-flow control is enabled in UART function mode.\nNote2: This RTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LEV_RTS : RTS Pin Active Level\nThis bit defines the active level state of RTS pin output.\nNote1: Refer to Figure 6100 and Figure 6101 for UART function mode.\nNote2: Refer to Figure 6105 and Figure 6106 for RS-485 function mode.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTS_ST : RTS Pin Status (Read Only)\nThis bit mirror from RTS pin output of voltage logic status.\n
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

DCTSF : Detect CTS State Change Flag\nThis bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when MODEM_IEN (UA_IER [3]) is set to 1.\nNote: This bit is cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CTS_ST : CTS Pin Status (Read Only)\nThis bit mirror from CTS pin input of voltage logic status.\nNote: This bit echoes when UART Controller peripheral clock is enabled, and CTS multi-function port is selected.
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

LEV_CTS : CTS Pin Active Level\nThis bit defines the active level state of CTS pin input.\nNote: Refer to Figure 699 for more information.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RX_OVER_IF : RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size, 16 bytes this bit will be set.\nNote: This bit is cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RS485_ADD_DETF : RS-485 Address Byte Detection Flag\nNote1: This field is used for RS-485 function mode.\nNote2: This bit is cleared by writing 1 to it.
bits : 3 - 3 (1 bit)
access : read-write

PEF : Parity Error Flag (Read Only) This bit is set to logic 1 whenever the received character does not have a valid parity bit . Note1: This bit is read only, but can be cleared by writing '1' to it . Note2: This bit is read only, but can be cleared by writing '1' to RFR (UA_FCR [1]) (Available on M05xxBN and M05xxDN/DE).
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

FEF : Framing Error Flag (Read Only) This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0). Note1: This bit is read only, but can be cleared by writing '1' to it . Note2: This bit is read only, but can be cleared by writing '1' to RFR (UA_FCR [1]) (Available on M05xxBN and M05xxDN/DE).
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

BIF : Break Interrupt Flag (Read Only) This bit is set to logic 1 whenever the received data input (RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). Note1: This bit is read only, but can be cleared by writing '1' to it . Note2: This bit is read only, but can be cleared by writing '1' to RFR (UA_FCR [1]) (Available on M05xxBN and M05xxDN/DE).
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RX_POINTER : RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RX_POINTER increases one. When one byte of RX FIFO is read by CPU, RX_POINTER decreases one.\nThe Maximum value shown in RX_POINTER is 15. When the using level of RX FIFO Buffer equal to 16, the RX_FULL bit is set to 1 and RX_POINTER will show 0. As one byte of RX FIFO is read by CPU, the RX_FULL bit is cleared to 0 and RX_POINTER will show 15.
bits : 8 - 13 (6 bit)
access : read-only

RX_EMPTY : Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RX_FULL : Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise is cleared by hardware.
bits : 15 - 15 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TX_POINTER : TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR, TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TX_POINTER decreases one.\nThe Maximum value shown in TX_POINTER is 15. When the using level of TX FIFO Buffer equal to 16, the TX_FULL bit is set to 1 and TX_POINTER will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TX_FULL bit is cleared to 0 and TX_POINTER will show 15.
bits : 16 - 21 (6 bit)
access : read-only

TX_EMPTY : Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not empty).
bits : 22 - 22 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TX_FULL : Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise is cleared by hardware.
bits : 23 - 23 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TX_OVER_IF : TX Overflow Error Interrupt Flag\nIf TX FIFO (UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1.\nNote: This bit is cleared by writing 1 to it.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TE_FLAG : Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RDA_IF : Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDA_IF will be set. If RDA_IEN (UA_IER [0]) is enabled, the RDA interrupt will be generated. \nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL).
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

THRE_IF : Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THRE_IEN (UA_IER [1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty).
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RLS_IF : Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If RLS_IEN (UA_IER [2]) is enabled, the RLS interrupt will be generated.\nNote2: This bit is read only and reset to 0 when all bits of BIF, FEF, PEF and RS485_ADD_DETF are cleared.
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

MODEM_IF : MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF.
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TOUT_IF : Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If RTO_IEN (UA_IER [4]) is enabled, the Tout interrupt will be generated.\nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it.
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

BUF_ERR_IF : Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX/RX FIFO overflow flag (TX_OVER_IF or RX_OVER_IF) is set. On M05xxBN, this bit is also set when Break Interrupt Flag, Parity Error Flag or Frame Error Flag (BIF, PEF or FEF) is set.\nWhen BUF_ERR_IF is set, the transfer is not correct. If BUF_ERR_IEN (UA_IER [5]) is enabled, the buffer error interrupt will be generated.\nNote1: On M05xxDN/DE, this bit is read only and reset to 0 when all bits of TX_OVER_IF and RX_OVER_IF are cleared. \nNote2: On M05xxBN, this bit is read only and reset to 0 when all bits of TX_OVER_IF, RX_OVER_IF, BIF, FEF and PEF are cleared. (M05xxBN Only)
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

LIN_RX_BREAK_IF : LIN Bus RX Break Field Detected Flag\nThis bit is set when RX received LIN Break Field. If LIN_RX_BRK_IEN (UA_IER [8]) is enabled the LIN RX Break interrupt will be generated.\nNote: This bit is cleared by writing 1 to it.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RDA_INT : Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDA_IEN and RDA_IF are both set to 1.\n
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

THRE_INT : Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THRE_IEN and THRE_IF are both set to 1.\n
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RLS_INT : Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLS_IEN and RLS_IF are both set to 1.\n
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

MODEM_INT : MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEM_IEN and MODEM_IF are both set to 1.\n
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TOUT_INT : Time-out Interrupt Indicator (Read Only)\nThis bit is set if RTO_IEN and TOUT_IF are both set to 1.\n
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

BUF_ERR_INT : Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and BUF_ERR_IF are both set to 1.\n
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

LIN_RX_BREAK_INT : LIN Bus RX Break Field Detected Interrupt Indicator (Read Only)\nThis bit is set if LIN_RX_BRK_IEN and LIN_RX_BREAK_IF are both set to 1.\n
bits : 15 - 15 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TOIC : Time-out Interrupt Comparator\n
bits : 0 - 7 (8 bit)
access : read-write

DLY : TX Delay Time Value \nThis field is use to programming the transfer delay time between the last stop bit and next start bit.
bits : 8 - 15 (8 bit)
access : read-write

BRD : Baud Rate Divider\nThe field indicated the baud rate divider.
bits : 0 - 15 (16 bit)
access : read-write

DIVIDER_X : Divider X\n
bits : 24 - 27 (4 bit)
access : read-write

DIV_X_ONE : Divider X Equal 1\nNote1: Refer to the section 6.14.5.1 for more information.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DIV_X_EN : Divider X Enable Control\nNote1: Refer to the section 6.14.5.1 for more information.\nNote2: In IrDA function mode, this bit must disable.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TX_SELECT : IrDA Receiver Enable Control\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INV_TX : Inverse RX Output Control\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INV_RX : Inverse RX Input Control\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UA_LIN_BKFL : UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote: This break field length is UA_LIN_BKFL + 2.
bits : 0 - 3 (4 bit)
access : read-write

LIN_RX_EN : LIN RX Enable Control \n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LIN_TX_EN : LIN TX Break Mode Enable Control\nNote: When TX break field transfer operation finished, this bit will be cleared automatically.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RS485_NMM : RS-485 Normal Multi-drop Operation Mode (NMM) Control\nNote: It cannot be active with RS485_AAD operation mode.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RS485_AAD : RS-485 Auto Address Detection Operation Mode (AAD) Control\nNote: It cannot be active with RS485_NMM operation mode.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RS485_AUD : RS-485 Auto Direction Mode (AUD) Control\nNote: It can be active with RS485_AAD or RS485_NMM operation mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RS485_ADD_EN : RS-485 Address Detection Enable Control\nThis bit is use to enable RS-485 Address Detection mode.\nNote: This field is used for RS-485 any operation mode.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADDR_MATCH : Address Match Value Register\nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode.
bits : 24 - 31 (8 bit)
access : read-write

FUN_SEL : Function Select\nUART Controller function mode selection.\n
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RDA_IEN : Receive Data Available Interrupt Enable Control\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

THRE_IEN : Transmit Holding Register Empty Interrupt Enable Control\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RLS_IEN : Receive Line Status Interrupt Enable Control\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODEM_IEN : Modem Status Interrupt Enable Control\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTO_IEN : RX Time-out Interrupt Enable Control\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUF_ERR_IEN : Buffer Error Interrupt Enable Control\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WAKE_EN : UART Wake-up Function Enable Control\nNote: when the chip is in Power-down mode, an external CTS change will wake-up chip from Power-down mode.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LIN_RX_BRK_IEN : LIN RX Break Field Detected Interrupt Enable Control\nNote: This bit is used for LIN function mode.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIME_OUT_EN : Time-out counter Enable Control\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AUTO_RTS_EN : RTS Auto-Flow Control Enable Control\nNote: When RTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTS_TRI_LEV (UA_FCR [19:16]), the UART will reassert RTS signal.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AUTO_CTS_EN : CTS Auto-Flow Control Enable Control\nNote: When CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted).
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RFR : RX Field Software Reset\nWhen RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART Controller peripheral clock cycles.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TFR : TX Field Software Reset\nWhen TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART Controller peripheral clock cycles.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RFITL : RX FIFO Interrupt (RDA_INT) Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL then the RDA_IF will be set (if RDA_IEN in UA_IER register is enable, an interrupt will generated).\n
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RX_DIS : Receiver Disable Register\nThe receiver is disabled or not (set 1 to disable receiver)\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before RS-485_NMM (UA_ALT_CSR [8]) is programmed.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTS_TRI_LEV : RTS Trigger Level (for Auto-flow Control Use)\nNote: This field is used for RTS auto-flow control.
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WLS : Word Length Selection\n
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

NSB : Number of STOP bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PBE : Parity Bit Enable Control\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EPE : Even Parity Enable Control\nThis bit has effect only when PBE (UA_LCR[3]) is set.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPE : Stick Parity Enable Control\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BCB : Break Control Bit\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic.\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.