\n
address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x100 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x80 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x180 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x300 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected
IRQ0 ~ IRQ31 Set-Enable Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA : Interrupt Enable\nThe ISER enables interrupts, and shows the interrupts that are enabled. Each bit represents an IRQ number from IRQ0 ~ IRQ31 (Exception number from 16 ~ 47).\nWrite:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nInterrupt Disabled
1 : 1
Interrupt Enabled
End of enumeration elements list.
IRQ0 ~ IRQ31 Set-Pending Control Register
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND : Interrupt set-pending.\nThe ISPR forces interrupts into the pending state, and shows the interrupts that are pending. Each bit represents an IRQ number from IRQ0 ~ IRQ31 (Exception number from 16 ~ 47).\nWrite:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
no effect.\ninterrupt is not pending
1 : 1
changes interrupt state to pending.\ninterrupt is pending
End of enumeration elements list.
IRQ0 ~ IRQ31 Clear-Pending Control Register
address_offset : 0x180 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRPEND : Interrupt clear-pending.\nThe ICPR removes the pending state from interrupts, and shows the interrupts that are pending. Each bit represents an IRQ number from IRQ0 ~ IRQ31 (Exception number from 16 ~ 47).\nWrite:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
no effect.\ninterrupt is not pending
1 : 1
removes pending state an interrupt.\ninterrupt is pending
End of enumeration elements list.
IRQ0 ~ IRQ3 Interrupt Priority Control Register
address_offset : 0x300 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : Priority of IRQ0\n'0' denotes the highest priority and '3' denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write
PRI_1 : Priority of IRQ1\n'0' denotes the highest priority and '3' denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write
PRI_2 : Priority of IRQ2\n'0' denotes the highest priority and '3' denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write
PRI_3 : Priority of IRQ3\n'0' denotes the highest priority and '3' denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write
IRQ4 ~ IRQ7 Interrupt Priority Control Register
address_offset : 0x304 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_4 : Priority of IRQ4\n'0' denotes the highest priority and '3' denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write
PRI_5 : Priority of IRQ5\n'0' denotes the highest priority and '3' denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write
PRI_6 : Priority of IRQ6\n'0' denotes the highest priority and '3' denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write
PRI_7 : Priority of IRQ7\n'0' denotes the highest priority and '3' denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write
IRQ8 ~ IRQ11 Interrupt Priority Control Register
address_offset : 0x308 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_8 : Priority of IRQ8\n'0' denotes the highest priority and '3' denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write
PRI_9 : Priority of IRQ9\n'0' denotes the highest priority and '3' denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write
PRI_10 : Priority of IRQ10\n'0' denotes the highest priority and '3' denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write
PRI_11 : Priority of IRQ11\n'0' denotes the highest priority and '3' denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write
IRQ12 ~ IRQ15 Interrupt Priority Control Register
address_offset : 0x30C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_12 : Priority of IRQ12\n'0' denotes the highest priority and '3' denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write
PRI_13 : Priority of IRQ13\n'0' denotes the highest priority and '3' denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write
PRI_14 : Priority of IRQ14\n'0' denotes the highest priority and '3' denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write
PRI_15 : Priority of IRQ15\n'0' denotes the highest priority and '3' denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write
IRQ16 ~ IRQ19 Interrupt Priority Control Register
address_offset : 0x310 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_16 : Priority of IRQ16\n'0' denotes the highest priority and '3' denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write
PRI_17 : Priority of IRQ17\n'0' denotes the highest priority and '3' denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write
PRI_18 : Priority of IRQ18\n'0' denotes the highest priority and '3' denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write
PRI_19 : Priority of IRQ19\n'0' denotes the highest priority and '3' denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write
IRQ20 ~ IRQ23 Interrupt Priority Control Register
address_offset : 0x314 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_20 : Priority of IRQ20\n'0' denotes the highest priority and '3' denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write
PRI_21 : Priority of IRQ21\n'0' denotes the highest priority and '3' denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write
PRI_22 : Priority of IRQ22\n'0' denotes the highest priority and '3' denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write
PRI_23 : Priority of IRQ23\n'0' denotes the highest priority and '3' denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write
IRQ24 ~ IRQ27 Interrupt Priority Control Register
address_offset : 0x318 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_24 : Priority of IRQ24\n'0' denotes the highest priority and '3' denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write
PRI_25 : Priority of IRQ25\n'0' denotes the highest priority and '3' denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write
PRI_26 : Priority of IRQ26\n'0' denotes the highest priority and '3' denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write
PRI_27 : Priority of IRQ27\n'0' denotes the highest priority and '3' denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write
IRQ28 ~ IRQ31 Interrupt Priority Control Register
address_offset : 0x31C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_28 : Priority of IRQ28\n'0' denotes the highest priority and '3' denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write
PRI_29 : Priority of IRQ29\n'0' denotes the highest priority and '3' denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write
PRI_30 : Priority of IRQ30\n'0' denotes the highest priority and '3' denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write
PRI_31 : Priority of IRQ31\n'0' denotes the highest priority and '3' denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write
IRQ0 ~ IRQ31 Clear-Enable Control Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRENA : Interrupt Clear Enable\nThe ICER disables interrupts, and shows the interrupts that are enabled. Each bit represents an IRQ number from IRQ0 ~ IRQ31 (Exception number from 16 ~ 47).\nWrite:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nInterrupt Disabled
1 : 1
Interrupt Disabled.\nInterrupt Enabled
End of enumeration elements list.
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.