\n
address_offset : 0x0 Bytes (0x0)
size : 0x88 byte (0x0)
mem_usage : registers
protection : not protected
IRQ0 (BOD) interrupt source identity
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BOD_INT : Identify BOD interrupt source.
bits : 0 - 0 (1 bit)
access : read-only
IRQ4 (P0-P4) interrupt source identity
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P0_INT : Identify P0 interrupt source.
bits : 0 - 0 (1 bit)
access : read-only
P1_INT : Identify P1 interrupt source.
bits : 1 - 1 (1 bit)
access : read-only
P2_INT : Identify P2 interrupt source.
bits : 2 - 2 (1 bit)
access : read-only
P3_INT : Identify P3 interrupt source.
bits : 3 - 3 (1 bit)
access : read-only
P4_INT : Identify P4 interrupt source.
bits : 4 - 4 (1 bit)
access : read-only
IRQ5 (P5-PA) interrupt source identity
address_offset : 0x14 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P5_INT : Identify P5 interrupt source.
bits : 0 - 0 (1 bit)
access : read-only
P6_INT : Identify P6 interrupt source.
bits : 1 - 1 (1 bit)
access : read-only
P7_INT : Identify P7 interrupt source.
bits : 2 - 2 (1 bit)
access : read-only
P8_INT : Identify P8 interrupt source.
bits : 3 - 3 (1 bit)
access : read-only
P9_INT : Identify P9 interrupt source.
bits : 4 - 4 (1 bit)
access : read-only
PA_INT : Identify PA interrupt source.
bits : 5 - 5 (1 bit)
access : read-only
IRQ6 (BPWM) interrupt source identity
address_offset : 0x18 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BPWM0_INT : Identify BPWM0 interrupt source.
bits : 0 - 0 (1 bit)
access : read-only
BPWM1_INT : Identify BPWM1 interrupt source.
bits : 1 - 1 (1 bit)
access : read-only
IRQ7 (ADC0) interrupt source identity
address_offset : 0x1C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADC0_INT : Identify ADC0 interrupt source.
bits : 0 - 0 (1 bit)
access : read-only
IRQ8 (TMR0) interrupt source identity
address_offset : 0x20 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TMR0_INT : Identify TMR0 interrupt source.
bits : 0 - 0 (1 bit)
access : read-only
IRQ9 (TMR1) interrupt source identity
address_offset : 0x24 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TMR1_INT : Identify TMR1 interrupt source.
bits : 0 - 0 (1 bit)
access : read-only
IRQ10 (TMR2) interrupt source identity
address_offset : 0x28 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TMR2_INT : Identify TMR2 interrupt source.
bits : 0 - 0 (1 bit)
access : read-only
IRQ11 (TMR3) interrupt source identity
address_offset : 0x2C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TMR3_INT : Identify TMR3 interrupt source.
bits : 0 - 0 (1 bit)
access : read-only
IRQ12 (UART0) interrupt source identity
address_offset : 0x30 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UART0_INT : Identify UART0 interrupt source.
bits : 0 - 0 (1 bit)
access : read-only
IRQ13 (UART1) interrupt source identity
address_offset : 0x34 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UART1_INT : Identify UART1 interrupt source.
bits : 0 - 0 (1 bit)
access : read-only
IRQ14 (SPI0) interrupt source identity
address_offset : 0x38 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SPI0_INT : Identify SPI0 interrupt source.
bits : 0 - 0 (1 bit)
access : read-only
IRQ15 (SPI1) interrupt source identity
address_offset : 0x3C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SPI1_INT : Identify SPI1 interrupt source.
bits : 0 - 0 (1 bit)
access : read-only
IRQ1 (WDT) interrupt source identity
address_offset : 0x4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WDT_INT : Identify WDT interrupt source.
bits : 0 - 0 (1 bit)
access : read-only
IRQ16 (SPI2) interrupt source identity
address_offset : 0x40 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SPI2_INT : Identify SPI2 interrupt source.
bits : 0 - 0 (1 bit)
access : read-only
IRQ17 (MDU) interrupt source identity
address_offset : 0x44 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MDU_INT : Identify MDU interrupt source.
bits : 0 - 0 (1 bit)
access : read-only
IRQ18 (I2C) interrupt source identity
address_offset : 0x48 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
I2C_INT : Identify I2C0 interrupt source.
bits : 0 - 0 (1 bit)
access : read-only
IRQ19 (Reserved) interrupt source identity
address_offset : 0x4C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ20 (CAN) interrupt source identity
address_offset : 0x50 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAN_INT : Identify CAN interrupt source.
bits : 0 - 0 (1 bit)
access : read-only
IRQ21 (EPWM0) interrupt source identity
address_offset : 0x54 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EPWM0_INT : Identify EPWM0 interrupt source.
bits : 0 - 0 (1 bit)
access : read-only
IRQ22 (EPWM1) interrupt source identity
address_offset : 0x58 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EPWM1_INT : Identify EPWM1 interrupt source.
bits : 0 - 0 (1 bit)
access : read-only
IRQ23 (CAP0) interrupt source identity
address_offset : 0x5C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAP0_INT : Identify CAP0 interrupt source.
bits : 0 - 0 (1 bit)
access : read-only
IRQ24 (CAP1) interrupt source identity
address_offset : 0x60 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAP1_INT : Identify CAP1 interrupt source.
bits : 0 - 0 (1 bit)
access : read-only
IRQ25 (ACMP) interrupt source identity
address_offset : 0x64 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ACMP_INT : Identify ACMP interrupt source.
bits : 0 - 0 (1 bit)
access : read-only
IRQ26 (QEI0) interrupt source identity
address_offset : 0x68 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
QEI0_INT : Identify QEI0 interrupt source.
bits : 0 - 0 (1 bit)
access : read-only
IRQ27 (QEI1) interrupt source identity
address_offset : 0x6C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
QEI1_INT : Identify QEI1 interrupt source.
bits : 0 - 0 (1 bit)
access : read-only
IRQ28 (PWRWU) interrupt source identity
address_offset : 0x70 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PWRWU_INT : Identify PWRWU interrupt source.
bits : 0 - 0 (1 bit)
access : read-only
IRQ29 (ADC1) interrupt source identity
address_offset : 0x74 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADC1_INT : Identify ADC1 interrupt source.
bits : 0 - 0 (1 bit)
access : read-only
IRQ30 (ADC2) interrupt source identity
address_offset : 0x78 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADC2_INT : Identify ADC2 interrupt source.
bits : 0 - 0 (1 bit)
access : read-only
IRQ31 (ADC3) interrupt source identity
address_offset : 0x7C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADC3_INT : Identify ADC3 interrupt source.
bits : 0 - 0 (1 bit)
access : read-only
IRQ2 (EINT0) interrupt source identity
address_offset : 0x8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EINT0 : Identify EINT0 interrupt source.\nEINT0 is external interrupt 0 from P3.2.
bits : 0 - 0 (1 bit)
access : read-only
NMI interrupt control register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NMI_SEL : NMI Interrupt Source Selection\nThe NMI interrupt to Cortex-M0 can be selected from one of IRQ0~IRQ31 by setting NMI_SEL with IRQ number. The default NMI interrupt is assigned as IRQ0 interrupt if NMI is enabled by setting NMI_SEL[8].
bits : 0 - 4 (5 bit)
access : read-write
NMI_EN : NMI Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
IRQ0~31 assigned to NMI Disabled. (NMI still can be software triggered by setting its pending flag.)
#1 : 1
IRQ0~31 assigned to NMI Enabled
End of enumeration elements list.
MCU interrupt request source register
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_IRQ : MCU IRQ Source Register\nThe MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0.\nThe MCU_IRQ collects all interrupts from each peripheral and synchronizes them and then interrupts the Cortex-M0.\nWhen the MCU_IRQ[n] is 0:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect
1 : 1
Generate an interrupt to Cortex_M0 NVIC[n].\nClear the interrupt and MCU_IRQ[n]
End of enumeration elements list.
IRQ3 (EINT1) interrupt source identity
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EINT1 : Identify EINT1 interrupt source.\nEINT1 is external interrupt from P3.3.
bits : 0 - 0 (1 bit)
access : read-only
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.