Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection : not protected
System Power Down Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XTL12M_EN : External 4~24 MHz Crystal Enable (Write-protection Bit)\nThe bit default value is set by flash controller user configuration register config0 [26:24]. When the default clock source is from external 4~24 MHz crystal, this bit is set to 1 automatically
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
External 4~24 MHz crystal Disabled
#1 : 1
External 4~24 MHz crystal Enabled
End of enumeration elements list.
OSC22M_EN : Internal 22.1184 MHz Oscillator Enable (Write-protection Bit)
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
22.1184 MHz Oscillation Disabled
#1 : 1
22.1184 MHz Oscillation Enabled
End of enumeration elements list.
OSC10K_EN : Internal 10 kHz Oscillator Enable (Write-protection Bit)
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
10 kHz Oscillation Disabled
#1 : 1
10 kHz Oscillation Enabled
End of enumeration elements list.
PD_WU_INT_EN : Power-down Mode Wake-up Interrupt Enable (Write-protection Bit)\nThe interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PD_WU_STS : Power-down Mode Wake-up Interrupt Status\nSet by 'power down wake up event', it indicates that resume from Power-down mode'\nWrite 1 to clear the bit to zero.
bits : 6 - 6 (1 bit)
access : read-write
Clock Source Select Control Register 0
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCLK_S : HCLK Clock Source Selection (Write-protection Bits)\nBefore clock switching, the related clock sources (both pre-select and new-select) must be turn on\nThe 3-bit default value is reloaded from the value of CFOSC (Config0[26:24]) in user configuration register of Flash controller by any reset. Therefore the default value is either 000b or 111b.\nThese bits are protected bit, It means programming this bit needs to write '59h', '16h', '88h' to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external 4~24 MHz crystal clock
#001 : 1
Reserved.
#010 : 2
Clock source from PLL clock
#011 : 3
Clock source from internal 10 kHz oscillator clock
#111 : 7
Clock source from internal 22.1184 MHz oscillator clock
End of enumeration elements list.
STCLK_S : Cortex_M0 SysTick Clock Source Selection (Write-protection Bits)
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external 4~24 MHz crystal clock
#001 : 1
Reserved.
#010 : 2
Clock source from external 4~24 MHz crystal clock/2
#011 : 3
Clock source from HCLK/2
#111 : 7
Clock source from internal 22.1184 MHz oscillator clock/2
End of enumeration elements list.
Clock Source Select Control Register 1
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDT_S : Watchdog Timer Clock Source Selection (Write-protection Bits)\nThese bits are protected bits, programing them need to write '59h', '16h', '88h' to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from HCLK/128 clock
#01 : 1
Clock source from HCLK/512 clock
#10 : 2
Clock source from HCLK/2048 clock
#11 : 3
Clock source from internal 10 kHz oscillator clock
End of enumeration elements list.
UART_S : UART Clock Source Selection
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from external 4~24 MHz crystal clock
#01 : 1
Clock source from PLL clock
#10 : 2
Reserved.
#11 : 3
Clock source from internal 22.1184 MHz oscillator clock
End of enumeration elements list.
Clock Divider Number Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCLK_N : HCLK Clock Divider
bits : 0 - 3 (4 bit)
access : read-write
UART_N : UART Clock Divider
bits : 8 - 11 (4 bit)
access : read-write
ADC_N : ADC clock divider.
bits : 16 - 23 (8 bit)
access : read-write
Clock Source Select Control Register 2
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRQDIV_S : Clock Divider Clock Source Selection
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from external 4~24 MHz crystal clock
#01 : 1
Reserved.
#10 : 2
Clock source from HCLK
#11 : 3
Clock source from internal 22.1184 MHz oscillator clock
End of enumeration elements list.
PLL Control Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FB_DV : PLL Feedback Divider Control Pins\nRefer to the formulas below the table.
bits : 0 - 8 (9 bit)
access : read-write
IN_DV : PLL Input Divider Control Pins\nRefer to the formulas below the table.
bits : 9 - 13 (5 bit)
access : read-write
OUT_DV : PLL Output Divider Control Pins\nRefer to the formulas below the table.
bits : 14 - 15 (2 bit)
access : read-write
PD : Power-down Mode
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL is in normal mode
#1 : 1
PLL is in power-down mode (default)
End of enumeration elements list.
BP : PLL Bypass Control
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL is in normal mode (default)
#1 : 1
PLL clock output is same as clock input (XTALin)
End of enumeration elements list.
OE : PLL OE (FOUT enable) Pin Control
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL FOUT enable
#1 : 1
PLL FOUT is fixed low
End of enumeration elements list.
PLL_SRC : PLL Source Clock Selection
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL source clock from external 4~24 MHz crystal
#1 : 1
PLL source clock from internal 22.1184 MHz oscillator
End of enumeration elements list.
Frequency Divider Control Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FSEL : Frequency Divider Output Selection Bits\nThe output formula is:\nwhere FFRQDIV_CLK is the input clock frequency, FCLKO is the clock divider output frequency and N is the 4-bit value in FSEL[3:0].
bits : 0 - 3 (4 bit)
access : read-write
DIVIDER_EN : Frequency Divider Enable Bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Frequency divider Disabled
#1 : 1
Frequency divider Enabled
End of enumeration elements list.
AHB Devices Clock Enable Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISP_EN : Flash ISP Controller Clock Enable Control
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flash ISP engine clock Disabled
#1 : 1
Flash ISP engine clock Enabled
End of enumeration elements list.
DIV_EN : Hardware Divider Controller Clock Enable Control
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Hardware Divider engine clock Disabled
#1 : 1
Hardware Divider engine clock Enabled
End of enumeration elements list.
APB Devices Clock Enable Control Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDT_EN : Watchdog Timer Clock Enable (Write-protection Bit)\nThis bit is the protected bit. It means programming this needs to write '59h', '16h', '88h' to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Watchdog Timer clock Disabled
#1 : 1
Watchdog Timer clock Enabled
End of enumeration elements list.
TMR0_EN : Timer0 Clock Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer0 clock Disabled
#1 : 1
Timer0 clock Enabled
End of enumeration elements list.
TMR1_EN : Timer1 Clock Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer1 clock Disabled
#1 : 1
Timer1 clock Enabled
End of enumeration elements list.
TMR2_EN : Timer2 Clock Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer2 clock Disabled
#1 : 1
Timer2 clock Enabled
End of enumeration elements list.
TMR3_EN : Timer3 Clock Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer3 clock Disabled
#1 : 1
Timer3 clock Enabled
End of enumeration elements list.
FDIV_EN : Frequency Divider Output Clock Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Frequency divider output clock Disabled
#1 : 1
Frequency divider output clock Enabled
End of enumeration elements list.
I2C_EN : I2C Clock Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C clock Disabled
#1 : 1
I2C clock Enabled
End of enumeration elements list.
SPI0_EN : SPI0 Clock Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI0 clock Disabled
#1 : 1
SPI0 clock Enabled
End of enumeration elements list.
SPI1_EN : SPI1 Clock Enable
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI1 clock Disabled
#1 : 1
SPI1 clock Enabled
End of enumeration elements list.
SPI2_EN : SPI2 Clock Enable
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI2 clock Disabled
#1 : 1
SPI2 clock Enabled
End of enumeration elements list.
UART0_EN : UART0 Clock Enable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART0 clock Disabled
#1 : 1
UART0 clock Enabled
End of enumeration elements list.
UART1_EN : UART1 clock enable.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART1 clock Disabled
#1 : 1
UART1 clock Enabled
End of enumeration elements list.
MDU_EN : MDU Clock Enable
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
MDU clock Disabled
#1 : 1
MDU clock Enabled
End of enumeration elements list.
BPWM_EN : Basic PWM Clock Enable
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Basic PWM clock Disabled
#1 : 1
Basic PWM clock Enabled
End of enumeration elements list.
EPWM0_EN : Enhanced PWM0 Clock Enable
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enhanced PWM0 clock Disabled
#1 : 1
Enhanced PWM0 clock Enabled
End of enumeration elements list.
EPWM1_EN : Enhanced PWM1 Clock Enable
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enhanced PWM1 clock Disabled
#1 : 1
Enhanced PWM1 clock Enabled
End of enumeration elements list.
ACMP_EN : Analog comparator Clock Enable
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Analog comparator clock Disabled
#1 : 1
Analog comparator clock Enabled
End of enumeration elements list.
CAN_EN : CAN Bus Controller Clock Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
CAN clock Disabled
#1 : 1
CAN clock Enabled
End of enumeration elements list.
CAP0_EN : Input Capture 0 Clock Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Input capture 0 clock Disabled
#1 : 1
Input capture 0 clock Enabled
End of enumeration elements list.
CAP1_EN : Input Capture 1 Clock Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Input capture 1 clock Disabled
#1 : 1
Input capture 1 clock Enabled
End of enumeration elements list.
ADC_EN : ADC Clock Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
ADC clock Disabled
#1 : 1
ADC clock Enabled
End of enumeration elements list.
OPA_EN : OPA0 and OPA1 Clock Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
OPA0 and OPA1 clock Disabled
#1 : 1
OPA0 and OPA1 clock Enabled
End of enumeration elements list.
QEI0_EN : QEI0 Clock Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
QEI0 clock Disabled
#1 : 1
QEI0 clock Enabled
End of enumeration elements list.
QEI1_EN : QEI1 Clock Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
QEI1 clock Disabled
#1 : 1
QEI1 clock Enabled
End of enumeration elements list.
Clock status monitor Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XTL_STB : External 4~24 MHz Crystal Clock Source Stable Flag\nThis bit is read only.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
External 4~24 MHz crystal clock is not stable or disabled
#1 : 1
External 4~24 MHz crystal clock is stable
End of enumeration elements list.
PLL_STB : PLL Clock Source Stable Flag\nThis bit is read only.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL clock is not stable or disabled
#1 : 1
PLL clock is stable
End of enumeration elements list.
OSC10K_STB : Internal 10k Hz Clock Source Stable Flag\nThis bit is read only.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal 10k Hz oscillator clock is not stable or disabled
#1 : 1
Internal 10k Hz oscillator clock is stable
End of enumeration elements list.
OSC22M_STB : Internal 22.1184M Hz Oscillator Clock Source Stable Flag\nThis bit is read only.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal 22.1184M Hz oscillator clock is not stable or disabled
#1 : 1
Internal 22.1184M Hz oscillator clock is stable
End of enumeration elements list.
CLK_SW_FAIL : Clock Switching Fail Flag (Write-protection Bit)\nThis bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1.\nWrite 1 to clear the bit to zero.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock switching success
#1 : 1
Clock switching failure
End of enumeration elements list.
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