\n
address_offset : 0x0 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
GPIO Port Bit Mode Control
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PMD0 : Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [n] pin is in Input mode
#01 : 1
GPIO port [n] pin is in Push-pull Output mode
#10 : 2
GPIO port [n] pin is in Open-drain Output mode
#11 : 3
GPIO port [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
PMD1 : Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [n] pin is in Input mode
#01 : 1
GPIO port [n] pin is in Push-pull Output mode
#10 : 2
GPIO port [n] pin is in Open-drain Output mode
#11 : 3
GPIO port [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
PMD2 : Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [n] pin is in Input mode
#01 : 1
GPIO port [n] pin is in Push-pull Output mode
#10 : 2
GPIO port [n] pin is in Open-drain Output mode
#11 : 3
GPIO port [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
PMD3 : Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [n] pin is in Input mode
#01 : 1
GPIO port [n] pin is in Push-pull Output mode
#10 : 2
GPIO port [n] pin is in Open-drain Output mode
#11 : 3
GPIO port [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
PMD4 : Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [n] pin is in Input mode
#01 : 1
GPIO port [n] pin is in Push-pull Output mode
#10 : 2
GPIO port [n] pin is in Open-drain Output mode
#11 : 3
GPIO port [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
PMD5 : Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [n] pin is in Input mode
#01 : 1
GPIO port [n] pin is in Push-pull Output mode
#10 : 2
GPIO port [n] pin is in Open-drain Output mode
#11 : 3
GPIO port [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
PMD6 : Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [n] pin is in Input mode
#01 : 1
GPIO port [n] pin is in Push-pull Output mode
#10 : 2
GPIO port [n] pin is in Open-drain Output mode
#11 : 3
GPIO port [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
PMD7 : Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [n] pin is in Input mode
#01 : 1
GPIO port [n] pin is in Push-pull Output mode
#10 : 2
GPIO port [n] pin is in Open-drain Output mode
#11 : 3
GPIO port [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
PMD8 : Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [n] pin is in Input mode
#01 : 1
GPIO port [n] pin is in Push-pull Output mode
#10 : 2
GPIO port [n] pin is in Open-drain Output mode
#11 : 3
GPIO port [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
PMD9 : Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [n] pin is in Input mode
#01 : 1
GPIO port [n] pin is in Push-pull Output mode
#10 : 2
GPIO port [n] pin is in Open-drain Output mode
#11 : 3
GPIO port [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
PMD10 : Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [n] pin is in Input mode
#01 : 1
GPIO port [n] pin is in Push-pull Output mode
#10 : 2
GPIO port [n] pin is in Open-drain Output mode
#11 : 3
GPIO port [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
PMD11 : Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [n] pin is in Input mode
#01 : 1
GPIO port [n] pin is in Push-pull Output mode
#10 : 2
GPIO port [n] pin is in Open-drain Output mode
#11 : 3
GPIO port [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
PMD12 : Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [n] pin is in Input mode
#01 : 1
GPIO port [n] pin is in Push-pull Output mode
#10 : 2
GPIO port [n] pin is in Open-drain Output mode
#11 : 3
GPIO port [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
PMD13 : Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [n] pin is in Input mode
#01 : 1
GPIO port [n] pin is in Push-pull Output mode
#10 : 2
GPIO port [n] pin is in Open-drain Output mode
#11 : 3
GPIO port [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
PMD14 : Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [n] pin is in Input mode
#01 : 1
GPIO port [n] pin is in Push-pull Output mode
#10 : 2
GPIO port [n] pin is in Open-drain Output mode
#11 : 3
GPIO port [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
PMD15 : Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [n] pin is in Input mode
#01 : 1
GPIO port [n] pin is in Push-pull Output mode
#10 : 2
GPIO port [n] pin is in Open-drain Output mode
#11 : 3
GPIO port [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
GPIO Port Pin Value
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PIN0 : Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 0 - 0 (1 bit)
access : read-only
PIN1 : Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 1 - 1 (1 bit)
access : read-only
PIN2 : Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 2 - 2 (1 bit)
access : read-only
PIN3 : Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 3 - 3 (1 bit)
access : read-only
PIN4 : Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 4 - 4 (1 bit)
access : read-only
PIN5 : Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 5 - 5 (1 bit)
access : read-only
PIN6 : Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 6 - 6 (1 bit)
access : read-only
PIN7 : Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 7 - 7 (1 bit)
access : read-only
GPIO Port De-bounce Enable
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBEN0 : Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bit[m] de-bounce function Disabled
#1 : 1
Bit[m] de-bounce function Enabled
End of enumeration elements list.
DBEN1 : Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bit[m] de-bounce function Disabled
#1 : 1
Bit[m] de-bounce function Enabled
End of enumeration elements list.
DBEN2 : Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bit[m] de-bounce function Disabled
#1 : 1
Bit[m] de-bounce function Enabled
End of enumeration elements list.
DBEN3 : Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bit[m] de-bounce function Disabled
#1 : 1
Bit[m] de-bounce function Enabled
End of enumeration elements list.
DBEN4 : Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bit[m] de-bounce function Disabled
#1 : 1
Bit[m] de-bounce function Enabled
End of enumeration elements list.
DBEN5 : Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bit[m] de-bounce function Disabled
#1 : 1
Bit[m] de-bounce function Enabled
End of enumeration elements list.
DBEN6 : Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bit[m] de-bounce function Disabled
#1 : 1
Bit[m] de-bounce function Enabled
End of enumeration elements list.
DBEN7 : Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bit[m] de-bounce function Disabled
#1 : 1
Bit[m] de-bounce function Enabled
End of enumeration elements list.
GPIO Port Interrupt Mode Select
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMD0 : Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge triggered interrupt
#1 : 1
Level triggered interrupt
End of enumeration elements list.
IMD1 : Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge triggered interrupt
#1 : 1
Level triggered interrupt
End of enumeration elements list.
IMD2 : Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge triggered interrupt
#1 : 1
Level triggered interrupt
End of enumeration elements list.
IMD3 : Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge triggered interrupt
#1 : 1
Level triggered interrupt
End of enumeration elements list.
IMD4 : Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge triggered interrupt
#1 : 1
Level triggered interrupt
End of enumeration elements list.
IMD5 : Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge triggered interrupt
#1 : 1
Level triggered interrupt
End of enumeration elements list.
IMD6 : Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge triggered interrupt
#1 : 1
Level triggered interrupt
End of enumeration elements list.
IMD7 : Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge triggered interrupt
#1 : 1
Level triggered interrupt
End of enumeration elements list.
GPIO Port Interrupt Enable
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IF_EN0 : Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Port n bit m low-level or falling edge interrupt Disabled
#1 : 1
Port n bit m low-level or falling edge interrupt Enabled
End of enumeration elements list.
IF_EN1 : Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Port n bit m low-level or falling edge interrupt Disabled
#1 : 1
Port n bit m low-level or falling edge interrupt Enabled
End of enumeration elements list.
IF_EN2 : Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Port n bit m low-level or falling edge interrupt Disabled
#1 : 1
Port n bit m low-level or falling edge interrupt Enabled
End of enumeration elements list.
IF_EN3 : Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Port n bit m low-level or falling edge interrupt Disabled
#1 : 1
Port n bit m low-level or falling edge interrupt Enabled
End of enumeration elements list.
IF_EN4 : Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Port n bit m low-level or falling edge interrupt Disabled
#1 : 1
Port n bit m low-level or falling edge interrupt Enabled
End of enumeration elements list.
IF_EN5 : Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Port n bit m low-level or falling edge interrupt Disabled
#1 : 1
Port n bit m low-level or falling edge interrupt Enabled
End of enumeration elements list.
IF_EN6 : Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Port n bit m low-level or falling edge interrupt Disabled
#1 : 1
Port n bit m low-level or falling edge interrupt Enabled
End of enumeration elements list.
IF_EN7 : Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Port n bit m low-level or falling edge interrupt Disabled
#1 : 1
Port n bit m low-level or falling edge interrupt Enabled
End of enumeration elements list.
IR_EN0 : Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Port n bit m high-level or rising edge interrupt Disabled
#1 : 1
Port n bit m high-level or rising edge interrupt Enabled
End of enumeration elements list.
IR_EN1 : Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Port n bit m high-level or rising edge interrupt Disabled
#1 : 1
Port n bit m high-level or rising edge interrupt Enabled
End of enumeration elements list.
IR_EN2 : Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Port n bit m high-level or rising edge interrupt Disabled
#1 : 1
Port n bit m high-level or rising edge interrupt Enabled
End of enumeration elements list.
IR_EN3 : Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Port n bit m high-level or rising edge interrupt Disabled
#1 : 1
Port n bit m high-level or rising edge interrupt Enabled
End of enumeration elements list.
IR_EN4 : Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Port n bit m high-level or rising edge interrupt Disabled
#1 : 1
Port n bit m high-level or rising edge interrupt Enabled
End of enumeration elements list.
IR_EN5 : Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Port n bit m high-level or rising edge interrupt Disabled
#1 : 1
Port n bit m high-level or rising edge interrupt Enabled
End of enumeration elements list.
IR_EN6 : Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Port n bit m high-level or rising edge interrupt Disabled
#1 : 1
Port n bit m high-level or rising edge interrupt Enabled
End of enumeration elements list.
IR_EN7 : Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Port n bit m high-level or rising edge interrupt Disabled
#1 : 1
Port n bit m high-level or rising edge interrupt Enabled
End of enumeration elements list.
GPIO Port Interrupt Source Flag
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IF_ISF0 : Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at Port x.\nNo effect
#1 : 1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
End of enumeration elements list.
IF_ISF1 : Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at Port x.\nNo effect
#1 : 1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
End of enumeration elements list.
IF_ISF2 : Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at Port x.\nNo effect
#1 : 1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
End of enumeration elements list.
IF_ISF3 : Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at Port x.\nNo effect
#1 : 1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
End of enumeration elements list.
IF_ISF4 : Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at Port x.\nNo effect
#1 : 1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
End of enumeration elements list.
IF_ISF5 : Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at Port x.\nNo effect
#1 : 1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
End of enumeration elements list.
IF_ISF6 : Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at Port x.\nNo effect
#1 : 1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
End of enumeration elements list.
IF_ISF7 : Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at Port x.\nNo effect
#1 : 1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
End of enumeration elements list.
GPIO Port Bit Off Digital Enable
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFD0 : Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
I/O digital input path Enabled
#1 : 1
I/O digital input path Disabled (digital input tied to low)
End of enumeration elements list.
OFFD1 : Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
I/O digital input path Enabled
#1 : 1
I/O digital input path Disabled (digital input tied to low)
End of enumeration elements list.
OFFD2 : Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
I/O digital input path Enabled
#1 : 1
I/O digital input path Disabled (digital input tied to low)
End of enumeration elements list.
OFFD3 : Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
I/O digital input path Enabled
#1 : 1
I/O digital input path Disabled (digital input tied to low)
End of enumeration elements list.
OFFD4 : Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
I/O digital input path Enabled
#1 : 1
I/O digital input path Disabled (digital input tied to low)
End of enumeration elements list.
OFFD5 : Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
I/O digital input path Enabled
#1 : 1
I/O digital input path Disabled (digital input tied to low)
End of enumeration elements list.
OFFD6 : Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
I/O digital input path Enabled
#1 : 1
I/O digital input path Disabled (digital input tied to low)
End of enumeration elements list.
OFFD7 : Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
I/O digital input path Enabled
#1 : 1
I/O digital input path Disabled (digital input tied to low)
End of enumeration elements list.
GPIO Port Data Output
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOUT0 : Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT1 : Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT2 : Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT3 : Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT4 : Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT5 : Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT6 : Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
DOUT7 : Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#1 : 1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
GPIO Port Data Output Write Mask
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMASK0 : Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding Pn_DOUT[m] bit can be updated
#1 : 1
Corresponding Pn_DOUT[m] bit protected
End of enumeration elements list.
DMASK1 : Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding Pn_DOUT[m] bit can be updated
#1 : 1
Corresponding Pn_DOUT[m] bit protected
End of enumeration elements list.
DMASK2 : Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding Pn_DOUT[m] bit can be updated
#1 : 1
Corresponding Pn_DOUT[m] bit protected
End of enumeration elements list.
DMASK3 : Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding Pn_DOUT[m] bit can be updated
#1 : 1
Corresponding Pn_DOUT[m] bit protected
End of enumeration elements list.
DMASK4 : Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding Pn_DOUT[m] bit can be updated
#1 : 1
Corresponding Pn_DOUT[m] bit protected
End of enumeration elements list.
DMASK5 : Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding Pn_DOUT[m] bit can be updated
#1 : 1
Corresponding Pn_DOUT[m] bit protected
End of enumeration elements list.
DMASK6 : Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding Pn_DOUT[m] bit can be updated
#1 : 1
Corresponding Pn_DOUT[m] bit protected
End of enumeration elements list.
DMASK7 : Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding Pn_DOUT[m] bit can be updated
#1 : 1
Corresponding Pn_DOUT[m] bit protected
End of enumeration elements list.
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