Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x2C Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x3C Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
EPWM Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWMMOD : PWM Mode Selection
bits : 0 - 1 (2 bit)
access : read-write
PWMDIV : PWM Clock Pre-divider Selection
bits : 2 - 3 (2 bit)
access : read-write
PWMI_EN : Enable PWM Interrupt
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flag PWMF Disabled to trigger PWM interrupt
#1 : 1
Flag PWMF Enabled to trigger PWM interrupt
End of enumeration elements list.
BRKI_EN : Enable Brake0 and Brak1 Interrupt
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flags BFK0 and BFK1 Disabled to trigger PWM interrupt
#1 : 1
Flags BKF0 and BKF1 Enabled to trigger PWM interrupt
End of enumeration elements list.
LOAD : Reload PWM period registers (PWMP) and PWM Duty Registers (PWM0~3) Control Bit\nNote2: This bit is written by software, cleared by hardware, and always read as 0.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action if written with 0. The value of PWM period register (PWMP) and PWM duty registers (PWMn0~PWMn3) are not loaded to PWM counter and Comparator registers
#1 : 1
Hardware will update the value of PWM period register (PWMP) and PWM duty registers (PWMn0~PWMn3) to PWM Counter and Comparator register at the time of PWM Counter matches PWMP in Edge- and Center-aligned modes or at the time of PWM Counter down counts with underflow in Center-aligned mode
End of enumeration elements list.
PWMRUN : Start PWMRUN Control Bit
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The PWM stops running
#1 : 1
The PWM counter starts running
End of enumeration elements list.
INT_TYPE : PWM Interrupt Type Selection Bit\nNote: This bit is effective when PWM is in Center-aligned mode only.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMF will be set if PWM counter underflow
#1 : 1
PWMF will be set if PWM counter matches PWMP register
End of enumeration elements list.
PWMINV : Inverse PWM Comparator Output\nWhen PWMINV is set to high the PWM comparator output signals will be inversed, therefore the PWM Duty (in percentage) is changed to (1-Duty) before PWMINV is set to high.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Not inverse PWM comparator output
#1 : 1
Inverse PWM comparator output
End of enumeration elements list.
CLRPWM : Clear PWM Counter Control Bit.\nNote: It is automatically cleared by hardware.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#1 : 1
Clear 16-bit PWM counter to 000H
End of enumeration elements list.
PWMTYPE : PWM Aligned Type Selection Bit.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge-aligned type
#1 : 1
Centre-aligned type
End of enumeration elements list.
GRP : Group bit
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
The signals timing of PWM0, PWM2 and PWM4 are independent
#1 : 1
Unify the signals timing of PWM0, PWM2 and PWM4 in the same phase which is controlled by PWM0
End of enumeration elements list.
INVBKP0 : Inverse BKP0 State
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
The state of pin BKPx0 is passed to the negative edge detector
#1 : 1
The inversed state of pin BKPx0 is passed to the negative edge detector
End of enumeration elements list.
INVBKP1 : Inverse BKP1 State
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The state of pin BKPx1 is passed to the negative edge detector
#1 : 1
The inversed state of pin BKPx1 is passed to the negative edge detector
End of enumeration elements list.
BKEN0 : BKPx0 Pin Trigger Brake Function0 Enable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMx Brake Function 0 Disabled
#1 : 1
PWMx Brake Function 0 Enabled
End of enumeration elements list.
BKEN1 : BKPx1 Pin Trigger Brake Function Enable
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMx Brake Function 1 Disabled
#1 : 1
PWMx Brake Function 1 Enabled
End of enumeration elements list.
BK1SEL : Brake Function 1 Source Selection
bits : 18 - 19 (2 bit)
access : read-write
BK0FILT : Brake 0 (BKPx0 pin) Edge Detector Filter Clock Selection
bits : 20 - 21 (2 bit)
access : read-write
BK1FILT : Brake 1 (BKPx1 pin) Edge Detector Filter Clock Selection
bits : 22 - 23 (2 bit)
access : read-write
CPO0BK_EN : Enable CPO0 Digital Output as Brake0 Source
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
CPO0 as one brake source in Brake 0 Disabled
#1 : 1
CPO0 as one brake source in Brake 0 Enabled
End of enumeration elements list.
CPO1BK_EN : Enable CPO1 Digital Output as Brake 0 Source
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
CPO1 as one brake source in Brake 0 Disabled
#1 : 1
CPO1 as one brake source in Brake 0 Enabled
End of enumeration elements list.
CPO2BK_EN : CPO2 Digital Output as Brake 0 Source Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
CPO2 as one brake source in Brake 0 Disabled
#1 : 1
CPO2 as one brake source in Brake 0 Enabled
End of enumeration elements list.
LVDBK_EN : Low-level Detection Trigger PWM Brake Function 1 Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brake Function 1 triggered by Low-level detection Disabled
#1 : 1
Brake Function 1 triggered by Low-level detection Enabled
End of enumeration elements list.
BK0NF_DIS : PWM Brake 0 Noise Filter Disable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Noise filter of PWM Brake 0 Enabled
#1 : 1
Noise filter of PWM Brake 0 Disabled
End of enumeration elements list.
BK1NF_DIS : PWM Brake 1 Noise Filter Disable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Noise filter of PWM Brake 1 Enabled
#1 : 1
Noise filter of PWM Brake 1 Disabled
End of enumeration elements list.
AUTOLD : Auto Load Enable Bit
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM duty registers PWMx0~PWMx4 are updated by software
#1 : 1
PWM duty registers PWMx0~PWMx4 are auto-load from motor drive unit (MDU) when MDU update a set of new duty values for PWM unit
End of enumeration elements list.
CLDMD : Center Reload Mode Enable\nThis bit only works when EPWM operating in Center-aligned mode.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM reload duty register at the period point of PWM counter
#1 : 1
EPWM reload duty register at the center point of PWM counter
End of enumeration elements list.
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Mask Mode Enable Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PMSKE : PWM Mask Enable Bit\nThe PWM generator signal will be masked when this bit is enabled. The corresponding PWMn channel will be output with PMD.n data.
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : 0
PWM generator signal is output to next stage
1 : 1
PWM generator signal is masked and PMD.n is output to next stage
End of enumeration elements list.
EPWM Mask Mode Data Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PMSKD : PWM Mask Data Bit
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : 0
Output logic low to PWMn
1 : 1
Output logic high to PWMn
End of enumeration elements list.
EPWM Dead-time Control Register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTCNT : Dead-time Counter\nThe dead-time can be calculated according to the following formula:
bits : 0 - 10 (11 bit)
access : read-write
DTEN0 : Enable Dead-time Insertion for PWMx Pair (PWM0, PWM1)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead-time insertion is inactive, the outputs of pin pair are complementary without any delay.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Dead-time insertion Disabled on the pin pair (PWM0, PWM1)
#1 : 1
Dead-time insertion Enabled on the pin pair (PWM0, PWM1)
End of enumeration elements list.
DTEN2 : Enable Dead-time Insertion for PWMx Pair (PWM2, PWM3)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead-time insertion is inactive, the outputs of pin pair are complementary without any delay.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Dead-time insertion Disabled on the pin pair (PWM2, PWM3)
#1 : 1
Dead-time insertion Enabled on the pin pair (PWM2, PWM3)
End of enumeration elements list.
DTEN4 : Enable Dead-time Insertion for PWMx Pair (PWM4, PWM5)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead-time insertion is inactive, the outputs of pin pair are complementary without any delay.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Dead-time insertion Disabled on the pin pair (PWM4, PWM5)
#1 : 1
Dead-time insertion Enabled on the pin pair (PWM4, PWM5)
End of enumeration elements list.
EPWM Brake Output
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWMB : PWM Brake Output\nWhen PWM Brake is asserted, the PWM0~5 output state before polarity control will follow PWMB bit0~5 setting, respectively.
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : 0
PWMn output before polarity control is low when Brake is asserted
1 : 1
PWMn output before polarity control is high when Brake is asserted
End of enumeration elements list.
EPWM Negative Polarity Control
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PNPn : PWM Negative Polarity Control\nThe register bit controls polarity/active state of real PWM output.
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : 0
PWMn output is active high
1 : 1
PWMn output is active low
End of enumeration elements list.
EPWMF Compared Counter
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWMFCNT : PWMF Compared Counter\nThe register sets the count number which defines how many times of PWM period occurs to set bit PWMF to request the PWM period interrupt. \nPWMF will be set in every (1 + PWMFCNT[3:0]) time of PWM period or center point defined by INT_TYPE at PWMCON[8] occurs
bits : 0 - 3 (4 bit)
access : read-write
EPWM Status Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKF0 : PWM Brake0 Flag\nNote: This bit must be cleared by writing 1 to itself through software.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Brake 0 is able to poll falling signal at BKP0 and has not recognized any one
#1 : 1
When PWM Brake 0 detects a falling signal at BKP0, this flag will be set to high
End of enumeration elements list.
BKF1 : PWM Brake1 Flag\nNote: This bit must be cleared by writing 1 to itself through software.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Brake 1 is able to poll falling signal at BKP1 and has not recognized any one
#1 : 1
When PWM Brake 1 detects a falling signal at pin BKP1, this flag will be set to high
End of enumeration elements list.
PWMF : PWM Period Flag.\nNote: This bit must be cleared by writing 1 to itself through software.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The PWM Counter has not up counted to the value of PWMP or down counted with underflow
#1 : 1
Hardware will set this flag to high at the time of PWM Counter matches PWMP in Edge- and Center-aligned modes or at the time of PWM Counter down counts with underflow in Center-aligned mode
End of enumeration elements list.
PWM0EF : PWMx0 Edge Flag\nNote: This bit must be cleared by writing 1 to itself through software.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMx0 not toggled
#1 : 1
Hardware will set this flag to high at the time of PWMx0 rising or falling. If EINT0_TYPE = 0, this bit is set when PWMx0 falling is detected. If EINT0_TYPE = 1, this bit is set when PWMx0 rising is detected
End of enumeration elements list.
PWM2EF : PWMx2 Edge Flag\nNote: This bit must be cleared by writing 1 to itself through software.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMx2 not toggled
#1 : 1
Hardware will set this flag to high at the time of PWMx2 rising or falling. If EINT2_TYPE = 0, this bit is set when PWMx2 falling is detected. If EINT2_TYPE = 1, this bit is set when PWMx2 rising is detected
End of enumeration elements list.
PWM4EF : PWMx4 Edge Flag\nNote: This bit must be cleared by writing 1 to itself through software.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMx4 not toggled
#1 : 1
Hardware will set this flag to high at the time of PWMx4 rising or falling. If EINT4_TYPE = 0, this bit is set when PWMx4 falling is detected. If EINT4_TYPE = 1, this bit is set when PWMx4 rising is detected
End of enumeration elements list.
BKLK0 : PWM Brake0 Locked \nNote: This bit must be cleared by writing 1 to itself through software.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brake 0 state is released
#1 : 1
When PWM Brake detects a falling signal at BKP0, this flag will be set to high to indicate the Brake0 state is locked
End of enumeration elements list.
BK0STS : Brake 0 Status (Read Only)
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
#0 : 0
PWM had been out of Brake 0 state
#1 : 1
PWM is in Brake 0 state
End of enumeration elements list.
BK1STS : Brake 1 Status (Read Only)
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
#0 : 0
PWM had been out of Brake 1 state
#1 : 1
PWM is in Brake 1 state
End of enumeration elements list.
EPWM Edge Interrupt Control Register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM0EI_EN : Enable PWMx0 Edge Interrupt
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flag PWM0EF Disabled to trigger PWM interrupt
#1 : 1
Flag PWM0EF Enabled to trigger PWM interrupt
End of enumeration elements list.
PWM2EI_EN : Enable PWMx2 Edge Interrupt
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flag PWM2EF Disabled to trigger PWM interrupt
#1 : 1
Flag PWM2EF Enabled to trigger PWM interrupt
End of enumeration elements list.
PWM4EI_EN : Enable PWMx4 Edge Interrupt
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flag PWM4EF Disabled to trigger PWM interrupt
#1 : 1
Flag PWM4EF Enabled to trigger PWM interrupt
End of enumeration elements list.
EINT0_TYPE : PWMx0 Edge Interrupt Type
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM0EF will be set if falling edge is detected at PWMx0
#1 : 1
PWM0EF will be set if rising edge is detected at PWMx0
End of enumeration elements list.
EINT2_TYPE : PWMx2 Edge Interrupt Type
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM2EF will be set if falling edge is detected at PWMx2
#1 : 1
PWM2EF will be set if rising edge is detected at PWMx2
End of enumeration elements list.
EINT4_TYPE : PWMx4 Edge Interrupt Type
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM4EF will be set if falling edge is detected at PWMx4
#1 : 1
PWM4EF will be set if rising edge is detected at PWMx4
End of enumeration elements list.
EPWM Period Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWMP : PWM Period Register\nEdge-aligned:
bits : 0 - 15 (16 bit)
access : read-write
EPWM PWM0 Duty Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_Duty : PWM Duty Register\nEdge-aligned:
bits : 0 - 15 (16 bit)
access : read-write
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