\n

MDU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x88 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x100 Bytes (0x0)
size : 0x3C byte (0x0)
mem_usage : registers
protection : not protected

Registers

Ia

Ibeta

PI_dMAX

PI_dMIN

PI_qMAX

PI_qMIN

I_dMAX

I_dMIN

I_qMAX

I_qMIN

Vd_In

Vq_In

PWMNORM

PWMMAX

PWMMIN

Id_Err

Iq_Err

SIN

COS

Id

Iq

Id_CMD

Iq_CMD

KP_d

KI_d

KP_q

KI_q

PI_dFW

Ib

PI_qFW

UI_d

UI_q

Vd

Vq

Valfa

Vbeta

Vref1

Vref2

Vref3

SVPDATA0

SVPDATA2

SVPDATA4

SVPDATA0N

SVPDATA2N

SVPDATA4N

Ic

MDUCON

MDUSTS

Ialfa


Ia

Phase A Current Register, Represented in Q-15 Format
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Ia Ia read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Motor Phase Current Data Register\nThis register stores the phase current data represented in Q-15 format. \nThe MCU must update registers Ia, Ib and Ic in the beginning of a FOC process flow.
bits : 0 - 15 (16 bit)
access : read-write


Ibeta


address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Ibeta Ibeta read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PI_dMAX

Maximum limit value of PI_d Controller in Q-15 Format
address_offset : 0x100 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PI_dMAX PI_dMAX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAX

MAX : Maximum Limit of PI Controller and I Controller Output\nThe 16-bit value represented in Q-15 format limits the maximum value of the PI controller and I controller output.
bits : 0 - 15 (16 bit)
access : read-write


PI_dMIN

Minimum limit value of PI_d Controller in Q-15 Format
address_offset : 0x104 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PI_dMIN PI_dMIN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIN

MIN : Minimum Limit of PI Controller and I Controller Output\nThe 16-bit value represented in Q-15 format limits the minimum value of the PI controller and I controller output.
bits : 0 - 15 (16 bit)
access : read-write


PI_qMAX


address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PI_qMAX PI_qMAX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PI_qMIN


address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PI_qMIN PI_qMIN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

I_dMAX

Maximum limit value of integral_d Controller in Q-15 Format
address_offset : 0x110 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I_dMAX I_dMAX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAX

MAX : Maximum Limit of PI Controller and I Controller Output\nThe 16-bit value represented in Q-15 format limits the maximum value of the integral controller output.
bits : 0 - 15 (16 bit)
access : read-write


I_dMIN

Minimum limit value of integral_d Controller in Q-15 Format
address_offset : 0x114 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I_dMIN I_dMIN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIN

MIN : Minimum Limit of PI Controller and I Controller Output\nThe 16-bit value represented in Q-15 format limits the minimum value of the integral controller output.
bits : 0 - 15 (16 bit)
access : read-write


I_qMAX


address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I_qMAX I_qMAX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

I_qMIN


address_offset : 0x11C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I_qMIN I_qMIN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Vd_In

Inverse Park Transformation Input of d_axis represented in Q-15 Format
address_offset : 0x120 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

Vd_In Vd_In read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Inverse Park Transformation Input Data (Read Only)\nThis data content is produced by the PI controller with maximum and minimum limit operation and stored in Q-15 format. It is a read only register
bits : 0 - 15 (16 bit)
access : read-only


Vq_In


address_offset : 0x124 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Vq_In Vq_In read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWMNORM

An Unsigned 16-bit PWM Normalization Value
address_offset : 0x128 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWMNORM PWMNORM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWMNORM

PWMNORM : PWM Normalization Data\nThe SVPWM function block will normalize the value of SVP0/2/4 to the range between 0000h and the value of PWMNORM and limit the PWM duty value within PWMMAX and PWMMIN. Here, the register content is a 16-bit unsigned integer.
bits : 0 - 15 (16 bit)
access : read-write


PWMMAX

An unsigned 16-bit Maximum Limit Value of SVPWM Output
address_offset : 0x12C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWMMAX PWMMAX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWMMAX

PWMMAX : Maximum Limit of SVPWM Output Data Register\nThe SVPWM function block will normalizes the value of SVP0/2/4 to the range between 0000h and the value of PWMNORM and limit the PWM duty value within PWMMAX and PWMMIN. Here, the register content is a 16-bit unsigned integer.
bits : 0 - 15 (16 bit)
access : read-write


PWMMIN

An unsigned 16-bit Minimum Limit Value of SVPWM Output
address_offset : 0x130 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWMMIN PWMMIN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWMMIN

PWMMIN : Maximum Limit of SVPWM Output Data Register\nThe SVPWM function block will normalize the value of SVP0/2/4 to the range between 0000h and the value of PWMNORM and limit the PWM duty value within PWMMAX and PWMMIN. Here, the register content is a 16-bit unsigned integer.
bits : 0 - 15 (16 bit)
access : read-write


Id_Err

Error of Id current = Id_CMD - Id Read only
address_offset : 0x134 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

Id_Err Id_Err read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Iq_Err

Error of Id current = Iq_CMD - Iq Read only.
address_offset : 0x138 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

Iq_Err Iq_Err read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SIN

Trigonometric Value of SIN Register, Represented in Q-15 Format
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SIN SIN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Trigonometric Value of SIN / COS Data Register\nThe trigonometric value of SIN and COS, which is represented in Q-15 format, must be preset before operating Park and inverse Park transformation.
bits : 0 - 15 (16 bit)
access : read-write


COS


address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COS COS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Id

Park Transformation Output Register, the Current Along d-axis.
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Id Id read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Park Transformation Output Data Register\nThis data content is produced by Park Transformation function block and stored in Q-15 format. It is also writable by software.
bits : 0 - 15 (16 bit)
access : read-write


Iq


address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Iq Iq read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Id_CMD

PI_d Controller Command Input Register, Represented in Q-15 Format.
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Id_CMD Id_CMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD

CMD : PI Controller Command Input Register\nThe register content stands for the PI controller command input. It must be normalized in Q-15 format.
bits : 0 - 15 (16 bit)
access : read-write


Iq_CMD


address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Iq_CMD Iq_CMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

KP_d

Parameter KP for PI_d Controller, Represented in 18-bit I2Q-15 (Q2.15) Format
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

KP_d KP_d read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : PI Controller Parameter Register\nThe KP_d and KP_q stand for the proportional parameter of PI controller, the KI_d and KI_q stand for the integral parameter of PI controller. The register data value must be stored in Q-15 format.
bits : 0 - 17 (18 bit)
access : read-write


KI_d


address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

KI_d KI_d read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

KP_q


address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

KP_q KP_q read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

KI_q


address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

KI_q KI_q read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PI_dFW

PI_d Controller Feed Forward Data Register
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PI_dFW PI_dFW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : PI Controller Feed Forward Data Register\nSoftware presets the feed forward value of the PI controller in this register.
bits : 0 - 15 (16 bit)
access : read-write


Ib


address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Ib Ib read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PI_qFW


address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PI_qFW PI_qFW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

UI_d

D-axis I Control Output Data Register
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UI_d UI_d read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Integral Controller Output Data Register\nThe PI function block content I (Integral) controller and P (Propotional) controller, and I controller output data will be used as the next PI control flow. Here is the register to save the output data of I controller and will update when PI controller finished once operation. Here, the register content is a Q-15 format value.
bits : 0 - 15 (16 bit)
access : read-write


UI_q


address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UI_q UI_q read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Vd

PI_d Controller Output of d-axis, Represented in Q-15 Format
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Vd Vd read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : PI Controller Output Data Register (Inverse Park Transformation Input)\nThis data content is produced by PI controller function block and stored in Q-15 format. It is also writable by software.
bits : 0 - 15 (16 bit)
access : read-write


Vq


address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Vq Vq read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Valfa

Inverse Park Transformation Output, the Voltage Along the alpha-axis
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Valfa Valfa read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Inverse Park Transformation Output Data Register\nThis data content is produced by inverse Park Transformation function block and stored in Q-15 format. It is also writable by software.
bits : 0 - 15 (16 bit)
access : read-write


Vbeta


address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Vbeta Vbeta read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Vref1

Inverse Clarke Transformation Output Register
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Vref1 Vref1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Inverse Clarke Transformation Output Data Register\nThis data content is produced by inverse Clarke Transformation function block and stored in Q-15 format. It is also writable by software.
bits : 0 - 15 (16 bit)
access : read-write


Vref2


address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Vref2 Vref2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Vref3


address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Vref3 Vref3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SVPDATA0

SVPWM output Data Register (it is an unsigned 16-bit value and denotes Taon time)
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SVPDATA0 SVPDATA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SVPWM Output Data Register\nThis data content is produced by SVPWM function block and stored in Q-15 format. It is also writable by software.
bits : 0 - 15 (16 bit)
access : read-write


SVPDATA2


address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SVPDATA2 SVPDATA2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SVPDATA4


address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SVPDATA4 SVPDATA4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SVPDATA0N

An unsigned16-bit data Normalizes SVPDATA0 to PWMNORM and within the limit between PWMMAX and PWMMIN
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SVPDATA0N SVPDATA0N read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Normalized SVPDATA Register\nThe SVPWM function block will normalizes the value of SVP0/2/4 to the range between 0000h and the value of PWMNORM and limit the PWM duty value within PWMMAX and PWMMIN. If SVPWM function block auto mode is active, each new SVPDATA0N/2N/4N will be reload to PWM unit 0 duty registers PWM0/2/4 after SVPWM operation is completed if PWMRUN and LOAD bits are enabled in PWM unit 0. Here, the register content is a 16-bit unsigned integer.
bits : 0 - 15 (16 bit)
access : read-write


SVPDATA2N


address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SVPDATA2N SVPDATA2N read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SVPDATA4N


address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SVPDATA4N SVPDATA4N read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Ic


address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Ic Ic read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MDUCON

Motor Driver Unit Control Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDUCON MDUCON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CKSTR PKSTR PIDSTR PIQSTR INVPKSTR INVCKSTR SVPWMSTR PKAUTO PIDAUTO PIQAUTO INVPKAUTO INVCKAUTO SVPWMAUTO ATCLRFG SVPWM_DIS CK_IE PK_IE PID_IE PIQ_IE INVPK_IE INVCK_IE SVPWM_IE MDU_IE

CKSTR : Clarke Transformation Start Bit (Write Only, Read 0)\nSetting this bit to high will start proceeding Clarke Transformation and it is automatically cleared when the transform process is completed by hardware. Writing it to 0 will stop and reset the function block.
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

#0 : 0

No action

#1 : 1

Start the process

End of enumeration elements list.

PKSTR : Park Transformation Start Bit (Write Only, Read 0)\nSetting this bit to high will start proceeding Park Transformation and it is automatically cleared when the transform process is completed by hardware. Writing it to 0 will stop and reset the function block.
bits : 1 - 1 (1 bit)
access : write-only

Enumeration:

#0 : 0

No action

#1 : 1

Start the process

End of enumeration elements list.

PIDSTR : D-axis PI Controller Start Bit (Write Only, Read 0)\nSetting this bit to high will start proceeding D-axis PI Control and it is automatically cleared when the process is completed by hardware. Writing it to 0 will stop and reset the function block.
bits : 2 - 2 (1 bit)
access : write-only

Enumeration:

#0 : 0

No action

#1 : 1

Start the process

End of enumeration elements list.

PIQSTR : Q-axis PI Controller Start Bit (Write Only, Read 0)\nSetting this bit to high will start proceeding Q-axis PI Control and it is automatically cleared when the process is completed by hardware. Writing it to 0 will stop and reset the function block.
bits : 3 - 3 (1 bit)
access : write-only

Enumeration:

#0 : 0

No action

#1 : 1

Start the process

End of enumeration elements list.

INVPKSTR : Inverse Park Transformation Start Bit (Write Only, Read 0)\nSetting this bit to high will start proceeding Inverse Park Transformation and it is automatically cleared when the transform process is completed by hardware. Writing it to 0 will stop and reset the function block.
bits : 4 - 4 (1 bit)
access : write-only

Enumeration:

#0 : 0

No action

#1 : 1

Start the process

End of enumeration elements list.

INVCKSTR : Inverse Clarke Transformation Start Bit (Write Only, Read 0)\nSetting this bit to high will start proceeding Inverse Clarke Transformation and it is automatically cleared when the transform process is completed by hardware. Writing it to 0 will stop and reset the function block.
bits : 5 - 5 (1 bit)
access : write-only

Enumeration:

#0 : 0

No action

#1 : 1

Start the process

End of enumeration elements list.

SVPWMSTR : SVPWM Start Bit (Write Only, Read 0)\nSetting this bit to high will start proceeding SVPWM timing calculating and it is automatically cleared when the process is completed by hardware. Writing it to 0 will stop and reset the function block.
bits : 6 - 6 (1 bit)
access : write-only

Enumeration:

#0 : 0

No action

#1 : 1

Start the process

End of enumeration elements list.

PKAUTO : Park Transformation Auto-mode Enable Bit\nSetting this bit will enable auto-mode of the function block. If the auto-mode is active, the current function block is allowed to accept the previous start trigger and will trigger the start bit of the next function block after current function is completed.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Auto-mode Disabled

#1 : 1

Auto-mode Enabled

End of enumeration elements list.

PIDAUTO : D-axis PI Controller Auto-mode Enable Bit\nSetting this bit will enable auto-mode of the function block. If the auto-mode is active, the current function block is allowed to accept the previous start trigger and will trigger the start bit of the next function block after current function is completed.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Auto-mode Disabled

#1 : 1

Auto-mode Enabled

End of enumeration elements list.

PIQAUTO : D-axis PI Controller Auto-mode Enable Bit\nSetting this bit will enable auto-mode of the function block. If the auto-mode is active, the current function block is allowed to accept the previous start trigger and will trigger the start bit of the next function block after current function is completed.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Auto-mode Disabled

#1 : 1

Auto-mode Enabled

End of enumeration elements list.

INVPKAUTO : Inverse Park Transformation Auto-mode Enable Bit\nSetting this bit will enable auto-mode of the function block. If the auto-mode is active, the current function block is allowed to accept the previous start trigger and will trigger the start bit of the next function block after current function is completed.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Auto-mode Disabled

#1 : 1

Auto-mode Enabled

End of enumeration elements list.

INVCKAUTO : Inverse Clarke Transformation Auto-mode Enable Bit\nSetting this bit will enable auto-mode of the function block. If the auto-mode is active, the current function block is allowed to accept the previous start trigger and will trigger the start bit of the next function block after current function is completed.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

Auto-mode Disabled

#1 : 1

Auto-mode Enabled

End of enumeration elements list.

SVPWMAUTO : SVPWM Auto-mode Enable Bit\nSetting this bit will enable auto-mode of the function block. If the auto-mode is active, the SVPWM function block is allowed to accept the start trigger from Inverse Clarke block and SVPWM function proceeds completed, it will automatically update the duty registers in PWM unit0 and set the reload bit (LOAD).
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

Auto-mode Disabled

#1 : 1

Auto-mode Enabled

End of enumeration elements list.

ATCLRFG : Auto-Clear Flag Control Bit When this bit is set to high, the complete flag of each function block in auto-mode is cleared automatically after SVPWM function block has updated PWM duty registers. The auto-clear flag function helps the FOC control flow runs smoothly without the need of software clearing flags.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Auto-clear flag function Disabled

#1 : 1

Auto-clear flag function Enabled

End of enumeration elements list.

SVPWM_DIS : SVPWM Block Function Disable Bit
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

SVPWM function block produces the Space Vector PWM timing for PWM duty registers

#1 : 1

SVPWM operation Disabled

End of enumeration elements list.

CK_IE : Clark Block Interrupt Enable Bit
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clark block interrupt Disabled

#1 : 1

Clark block interrupt Enabled

End of enumeration elements list.

PK_IE : Park Block Interrupt Enable Bit
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

Park block interrupt Disabled

#1 : 1

Park block interrupt Enabled

End of enumeration elements list.

PID_IE : D-axis PI Block Interrupt Enable Bit
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

D-axis PI controller block interrupt Disabled

#1 : 1

D-axis PI controller block interrupt Enabled

End of enumeration elements list.

PIQ_IE : Q-axis PI Block Interrupt Enable Bit
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

Q-axis PI controller block interrupt Disabled

#1 : 1

Q-axis PI controller block interrupt Enabled

End of enumeration elements list.

INVPK_IE : Inv-Park Block Interrupt Enable Bit
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

Inv-Park block interrupt Disabled

#1 : 1

Inv-Park block interrupt Enabled

End of enumeration elements list.

INVCK_IE : Inv-Clark Block Interrupt Enable Bit
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

Inv-Clark block interrupt Disabled

#1 : 1

Inv-Clark block interrupt Enabled

End of enumeration elements list.

SVPWM_IE : Clark Block Interrupt Enable Bit
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

SVPWM block interrupt Disabled

#1 : 1

SVPWM block interrupt Enabled. Interrupt will generate if MDUINT_EN and SVPWM_IE is set to 1 and SVPWMCPF is set

End of enumeration elements list.

MDU_IE : MDU Interrupt Enable Bit
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

MDU interrupt Disabled

#1 : 1

MDU interrupt Enabled

End of enumeration elements list.


MDUSTS

Motor Driver Unit Status Register
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDUSTS MDUSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CKCPF PKCPF PI_qCPF PI_dCPF INVPKCPF INVCKCPF SVPWMCPF ZONE

CKCPF : Clarke Transformation Complete Flag\nWhen the function block completes the process, the corresponding complete flag will be set by hardware. This flag can be cleared by a writing one to itself.\nNote: If both the control bits ATCLRFG (Auto-clear flag control bit) and CKAUTO (Auto-mode enable bit) are set to high, the complete flag is cleared automatically after SVPWM function block has set PWM LOAD bit to high.
bits : 0 - 0 (1 bit)
access : read-write

PKCPF : Park Transformation Complete Flag\nWhen the function block completes the process, the corresponding complete flag will be set by hardware. This flag can be cleared by a writing one to itself.\nNote: If both the control bits ATCLRFG (Auto-clear flag control bit) and PKAUTO (Auto-mode enable bit) are set to high, the complete flag is cleared automatically after SVPWM function block has set PWM LOAD bit to high.
bits : 1 - 1 (1 bit)
access : read-write

PI_qCPF : PI_q Controller Complete Flag\nWhen the function block completes the process, the corresponding complete flag will be set by hardware. This flag can be cleared by a writing one to itself.\nNote: If both the control bits ATCLRFG (Auto-clear flag control bit) and PI_qAUTO (Auto-mode enable bit) are set to high, the complete flag is cleared automatically after SVPWM function block has set PWM LOAD bit to high.
bits : 2 - 2 (1 bit)
access : read-write

PI_dCPF : PI_d Controller Complete Flag\nWhen the function block completes the process, the corresponding complete flag will be set by hardware. This flag can be cleared by a writing one to itself.\nNote: If both the control bits ATCLRFG (Auto-clear flag control bit) and PI_dAUTO (Auto-mode enable bit) are set to high, the complete flag is cleared automatically after SVPWM function block has set PWM LOAD bit to high.
bits : 3 - 3 (1 bit)
access : read-write

INVPKCPF : Inverse Park Transformation Complete Flag\nWhen the function block completes the process, the corresponding complete flag will be set by hardware. This flag can be cleared by a writing one to itself.\nNote: If both the control bits ATCLRFG (Auto-clear flag control bit) and INVPKAUTO (Auto-mode enable bit) are set to high, the complete flag is cleared automatically after SVPWM function block has set PWM LOAD bit to high.
bits : 4 - 4 (1 bit)
access : read-write

INVCKCPF : Inverse Clarke Transformation Complete Flag\nWhen the function block completes the process, the corresponding complete flag will be set by hardware. This flag can be cleared by a writing one to itself.\nNote: If both the control bits ATCLRFG (Auto-clear flag control bit) and INVCKAUTO (Auto-mode enable bit) are set to high, the complete flag is cleared automatically after SVPWM function block has set PWM LOAD bit to high.
bits : 5 - 5 (1 bit)
access : read-write

SVPWMCPF : SVPWM Complete Flag\nWhen the function block completes the process, the corresponding complete flag will be set by hardware. This flag can be cleared by a writing one to itself.\nNote: If both the control bits ATCLRFG (Auto-clear flag control bit) and SVPWMAUTO (Auto-mode enable bit) are set to high, the complete flag is cleared automatically after SVPWM function block has set PWM LOAD bit to high.
bits : 6 - 6 (1 bit)
access : read-write

ZONE : Zone Number Indicator\nA 360 degree space is equally divided into six zones where each zone is with 60 degree space. The SVPWM function block will internally produce the zone number during the operation which indicates the which zone the motor electric angle stays in the moment.
bits : 8 - 10 (3 bit)
access : read-write


Ialfa

Clarke Transformation Output Register, the Current Along alpha-axis
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Ialfa Ialfa read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Clarke Transformation Output Data Register\nThis data content is produced by Clarke Transformation function block and stored in Q-15 format. It is also writable by software.
bits : 0 - 15 (16 bit)
access : read-write



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