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MDU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

Registers

MDUSCON

MDUSSTS


MDUSCON

MDU Switch Control
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDUSCON MDUSCON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDUS

MDUS : MDU Switch Control Register
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

MDU is controlled by MDU0 control register

#1 : 1

MDU is controlled by MDU1 control register

End of enumeration elements list.


MDUSSTS

MDU Switch Status
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDUSSTS MDUSSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDU0BUSY MDU1BUSY MDUACT

MDU0BUSY : MDU0 Busy Register
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

MDU0 is idle

#1 : 1

MDU0 is busy

End of enumeration elements list.

MDU1BUSY : MDU1 Busy Register
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

MDU1 is idle

#1 : 1

MDU1 is busy

End of enumeration elements list.

MDUACT : MDU Active Set
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

MDU0 is active

#1 : 1

MDU1 is active

End of enumeration elements list.



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