CAP_CNT

CAP_CNTCMP

CAP_CTR0

CAP_CTR1

CAP_STS

CAP_HLD0

CAP_HLD1

CAP_HLD2

CAP_CNT : Input Capture Timer/Counter\nThe input Capture Timer/Counter is a 24-bit up-counting counter. The clock source for the counter is from the clock divider output which the CAP_CLK is software optionally divided by 1,4,16 or 32.
bits : 0 - 23 (24 bit)
access : read-write

CAP_CNTCMP : Input Capture Counter Compare Register
bits : 0 - 23 (24 bit)
access : read-write

NFCLK_S : Noise Filter Clock Pre-divided Selection
bits : 0 - 1 (2 bit)
access : read-write

CAPNF_DIS : Disable Input Capture Noise Filter
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IC0_EN : Enable Port Pin IC0 Input to Input Capture Unit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IC1_EN : Enable Port Pin IC1 Input to Input Capture Unit
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IC2_EN : Enable Port Pin IC2 Input to Input Capture Unit
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPSEL0 : CAP0 Input Source Selection Bit
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPSEL1 : CAP1 Input Source Selection Bit
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPSEL2 : CAP2 Input Source Selection Bit
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPTF0_IEN : Enable Input Capture Channel 0 Interrupt
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPTF1_IEN : Enable Input Capture Channel 1 Interrupt
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPTF2_IEN : Enable Input Capture Channel 2 Interrupt
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPOV_IEN : Enable CAPOVF Trigger Input Capture Interrupt
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPCMP_IEN : Enable CAPCMPF Trigger Input Capture Interrupt
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPTST : Input Capture Counter Start Bit\nSetting this bit to 1, the capture counter (CAP_CNT) starts up-counting synchronously with capture clock input (CAP_CLK).
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPCLR : Input Capture Counter Clear by Compare-match Control Bit
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPTCLR : Input Capture Counter Clear by Capture Events Control Bit\nIf this bit is set to 1, the capture counter (CAP_CNT) will be cleared to 0 when any one of capture events (CAPTF0~3) occurs.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RLD_EN : The Reload Function Enable Bit\nSetting this bit to enable reload function. If the reload control is enabled, an overflow event (CAPOVF) or capture events (CAPTFx) will trigger the hardware to reload CAP_CNTCMP into CAP_CNT.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMP_EN : The Compare Function Enable Bit\nThe compare function in input capture timer/counter is to compare the dynamic counting CAP_CNT with the compare register CAP_CNTCMP, if CAP_CNT value reaches CAP_CNTCMP, the flag CAPCMPF will be set.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAP_EN : Input Capture Timer/Counter Enable Bit
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPEDG0 : Channel 0 Captured Edge Selection
bits : 0 - 1 (2 bit)
access : read-write

CAPEDG1 : Channel 1 Captured Edge Selection
bits : 2 - 3 (2 bit)
access : read-write

CAPEDG2 : Channel 2 Captured Edge Selection
bits : 4 - 5 (2 bit)
access : read-write

CPRLD_S : CAPCNT Reload Trigger Source Selection
bits : 8 - 10 (3 bit)
access : read-write

CAPDIV : Capture Timer Clock Divide Selection
bits : 12 - 13 (2 bit)
access : read-write

CAPCNT_SRC : Capture Timer/Counter Clock Source Select
bits : 16 - 17 (2 bit)
access : read-write

CAPTF0 : Input Capture Channel 0 Captured Flag\nWhen the input capture channel 0 detects a valid edge change at CAP0 input, it will set flag CAPTF0 to high. \nNote: This bit is only cleared by writing 1 to itself through software.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPTF1 : Input Capture Channel 1 Captured Flag\nWhen the input capture channel 1 detects a valid edge change at CAP1 input, it will set flag CAPTF1 to high. \nNote: This bit is only cleared by writing 1 to itself through software.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPTF2 : Input Capture Channel 2 Captured Flag\nWhen the input capture channel 2 detects a valid edge change at CAP2 input, it will set flag CAPTF2 to high. \nNote: This bit is only cleared by writing 1 to itself through software.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPCMPF : Input Capture Compare-match Flag\nIf the input capture compare function is enabled, the flag is set by hardware while capture counter (CAP_CNT) up counts and reach to the CAP_CNTCMP value.\nNote: This bit is only cleared by writing 1 to itself through software.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPOVF : Input Capture Counter Overflow Flag\nFlag is set by hardware when input capture up counter (CAP_CNT) overflows from 0x00FF_FFFF to 0.\nNote: This bit is only cleared by writing 1 to itself through software.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAP_HLD : Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change, the CAPCNT value is latched into the corresponding holding register. Each input channel has itself holding register named by CAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
bits : 0 - 23 (24 bit)
access : read-write