\n
address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x2C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x14 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
QEI Pulse Counter
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QEI_CNT : Quadrature Encoder Pulse Counter\nA 24-bit up/down counter. When an effective phase pulse is detected, this counter is increased by one if the bit DIR in EQICTR is one or decreased by one if the bit DIR is 0. This register performs an integrator which count value is proportional to the encoder position. The pulse counter may be initialized to a predetermined value by one of three events occurs:
bits : 0 - 31 (32 bit)
access : read-write
QEI Pre-set Maximum Count Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QEI_MAXCNT : Quadrature Encoder Preset Maximum Count Register\nThis register value determined by user stores the maximum value which may be the number of the quadrature encoder pulses in a revolution for the QEI controller compare-counting mode.
bits : 0 - 31 (32 bit)
access : read-write
QEI Control Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NFCLK_S : Noise Filter Clock Pre-divided Selection
bits : 0 - 1 (2 bit)
access : read-write
QEINF_DIS : Disable QEI Controller Input Noise Filter
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The noise filter of QEI controller Enabled
#1 : 1
The noise filter of QEI controller Disabled
End of enumeration elements list.
QEA_EN : Enable QEA Input to QEI Controller
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The QEA input to QEI Controller Disabled
#1 : 1
The QEA input to QEI Controller Enabled
End of enumeration elements list.
QEB_EN : Enable QEB Input to QEI Controller
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The QEB input to QEI Controller Disabled
#1 : 1
The QEB input to QEI Controller Enabled
End of enumeration elements list.
IDX_EN : Enable IDX Input to QEI Controller
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The IDX input to QEI Controller Disabled
#1 : 1
The IDX input to QEI Controller Enabled
End of enumeration elements list.
QEIMODE : QEI Counting Mode Selection
bits : 8 - 9 (2 bit)
access : read-write
QEA_INV : Inverse QEA Input Polarity
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Not inverse QEA input polarity
#1 : 1
QEA input polarity is inversed to QEI controller
End of enumeration elements list.
QEB_INV : Inverse QEB Input Polarity
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Not inverse QEB input polarity
#1 : 1
QEB input polarity is inversed to QEI controller
End of enumeration elements list.
IDX_INV : Inverse IDX Input Polarity
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Not inverse IDX input polarity
#1 : 1
IDX input polarity is inversed to QEI controller
End of enumeration elements list.
OVUN_IEN : Enable OVUNF Trigger QEI Interrupt
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
The OVUNF can trigger QEI controller interrupt Disabled
#1 : 1
The OVUNF can trigger QEI controller interrupt Enabled
End of enumeration elements list.
DIR_IEN : Enable DIRF Trigger QEI Interrupt
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
The DIRF can trigger QEI controller interrupt Disabled
#1 : 1
The DIRF can trigger QEI controller interrupt Enabled
End of enumeration elements list.
CMP_IEN : Enable CMPF Trigger QEI Interrupt
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
The CMPF can trigger QEI controller interrupt Disabled
#1 : 1
The CMPF can trigger QEI controller interrupt Enabled
End of enumeration elements list.
IDX_IEN : Enable IDXF Trigger QEI Interrupt
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
The IDXF can trigger QEI interrupt Disabled
#1 : 1
The IDXF can trigger QEI interrupt Enabled
End of enumeration elements list.
HOLDBYT0 : Hold QEI_CNT by Timer 0
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
TISR0.TIF has no effect on HOLDCNT
#1 : 1
A rising edge of bit TISR0.TIF in timer 0 sets HOLDCNT to 1
End of enumeration elements list.
HOLDBYT1 : Hold QEI_CNT by Timer 1
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
TISR1.TIF has no effect on HOLDCNT
#1 : 1
A rising edge of bit TISR1.TIF in timer 1 sets HOLDCNT to 1
End of enumeration elements list.
HOLDBYT2 : Hold QEI_CNT by Timer 2
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
TISR2.TIF has no effect on HOLDCNT
#1 : 1
A rising edge of bit TISR2.TIF in timer 2 sets HOLDCNT to 1
End of enumeration elements list.
HOLDBYT3 : Hold QEI_CNT by Timer 3
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
TISR3.TIF has no effect on HOLDCNT
#1 : 1
A rising edge of bit TISR3.TIF in timer 3 sets HOLDCNT to 1
End of enumeration elements list.
HOLDCNT : Hold QEI_CNT Control Bit
When this bit is set from low to high, the QEI_CNT value is copied into QEI_CNTHLD. This bit may be set by writing 1 to itself through software or Timer0~Timer3 interrupt flag (TISTR.TIF).
Note: This bit is automatically cleared after QEI_CNTHLD holds QEI_CNT value.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
No operation
#1 : 1
QEI_CNT content captured and stored in QEI_CNTHLD
End of enumeration elements list.
IDXLAT : Index Latch QEI_CNT Enable Bit\nIf this bit is set to high, the QEI_CNT content will be latched into QEI_CNTILAT at every rising on signal CHX.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
The index signal latch QEI counter function Disabled
#1 : 1
The index signal latch QEI counter function Enabled
End of enumeration elements list.
IDXRLD_EN : Index Trigger QEI_CNT Reload Enable Bit
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
The reload function Disabled
#1 : 1
The QEI_CNT re-initialized by Index signal Enabled
End of enumeration elements list.
CMP_EN : The Compare Function Enable Bit\nThe compare function in QEI controller is to compare the dynamic counting QEPCNT with the compare register QEI_CNTCMP, if QEI_CNT value reaches QEI_CNTCMP, the flag CMPF will be set.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
The compare function Disabled
#1 : 1
The compare function Enabled
End of enumeration elements list.
QEI_EN : Quadrature Encoder Interface Controller Enable Bit
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
QEI controller function Disabled
#1 : 1
QEI controller function Enabled
End of enumeration elements list.
QEI Status Register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IDXF : IDX Detected Flag\nWhen the QEI controller detects a rising edge on signal CHX it will set flag IDXF to high.\nNote: This bit is only cleared by writing 1 to itself through software.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No rising edge detected on signal CHX
#1 : 1
A rising edge occurred on signal CHX
End of enumeration elements list.
CMPF : Compare-match Flag\nIf the QEI compare function is enabled, the flag is set by hardware while QEI counter up or down counts and reach to the QEI_CNTCMP value.\nNote: This bit is only cleared by writing 1 to itself through software.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
QEI counter does not match with QEI_CNTCMP value
#1 : 1
QEI counter counts to the same as QEI_CNTCMP value
End of enumeration elements list.
OVUNF : QEI Counter Overflow or Underflow Flag\nFlag is set by hardware while QEI_CNT overflows from 0xFFFF_FFFF to 0 in Free-counting mode or from the QEI_MAXCNT value to 0 in compare-counting mode. Similarly, the flag is set wile QEI counter underflows from 0 to 0xFFFF_FFFF or QEI_MAXCNT.\nNote: This bit is only cleared by writing 1 to itself through software.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No overflow or underflow occurred in QEI counter
#1 : 1
QEI counter occurred counting overflow or underflow
End of enumeration elements list.
DIRF : Direction Change Flag\nFlag is set by hardware while QEI counter counting direction is changed, software can clear this bit by writing a one to it.\nNote: This bit is only cleared by writing 1 to itself through software.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No change in QEI counter counting direction
#1 : 1
QEI counter counting direction is changed
End of enumeration elements list.
DIR : QEI Counter Counting Direction Indication Bit\nNote: This bit is set/reset by hardware according to the phase detection between CHA and CHB.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
QEI Counter is in down-counting
#1 : 1
QEI Counter is in up-counting
End of enumeration elements list.
QEI Pulse Counter Hold Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QEI_CNTHLD : Quadrature Encoder Pulse Counter Hold Register\nWhen bit HOLDCNT (QEIxCTR[24]) goes from low to high, the QEPCNT value is copied into QEPCNTHLD register.
bits : 0 - 31 (32 bit)
access : read-write
QEI Pulse Counter Index Latch Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QEI_CNTILAT : Quadrature Encoder Pulse Counter Index Latch Register\nWhen bit IDXF (QEI_STS[18]) is set, the QEPI_CNT value is copied into QEI_CNTILAT register.
bits : 0 - 23 (24 bit)
access : read-write
QEI Pulse Counter Compare Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QEI_CNTCMP : Quadrature Encoder Pulse Counter Compare Register
bits : 0 - 31 (32 bit)
access : read-write
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