QEI_CNT

QEI_MAXCNT

QEI_CTR

QEI_STS

QEI_CNTHLD

QEI_CNTILAT

QEI_CNTCMP

QEI_CNT : Quadrature Encoder Pulse Counter\nA 24-bit up/down counter. When an effective phase pulse is detected, this counter is increased by one if the bit DIR in EQICTR is one or decreased by one if the bit DIR is 0. This register performs an integrator which count value is proportional to the encoder position. The pulse counter may be initialized to a predetermined value by one of three events occurs:
bits : 0 - 31 (32 bit)
access : read-write

QEI_MAXCNT : Quadrature Encoder Preset Maximum Count Register\nThis register value determined by user stores the maximum value which may be the number of the quadrature encoder pulses in a revolution for the QEI controller compare-counting mode.
bits : 0 - 31 (32 bit)
access : read-write

NFCLK_S : Noise Filter Clock Pre-divided Selection
bits : 0 - 1 (2 bit)
access : read-write

QEINF_DIS : Disable QEI Controller Input Noise Filter
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

QEA_EN : Enable QEA Input to QEI Controller
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

QEB_EN : Enable QEB Input to QEI Controller
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IDX_EN : Enable IDX Input to QEI Controller
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

QEIMODE : QEI Counting Mode Selection
bits : 8 - 9 (2 bit)
access : read-write

QEA_INV : Inverse QEA Input Polarity
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

QEB_INV : Inverse QEB Input Polarity
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IDX_INV : Inverse IDX Input Polarity
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OVUN_IEN : Enable OVUNF Trigger QEI Interrupt
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DIR_IEN : Enable DIRF Trigger QEI Interrupt
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMP_IEN : Enable CMPF Trigger QEI Interrupt
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IDX_IEN : Enable IDXF Trigger QEI Interrupt
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HOLDBYT0 : Hold QEI_CNT by Timer 0
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HOLDBYT1 : Hold QEI_CNT by Timer 1
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HOLDBYT2 : Hold QEI_CNT by Timer 2
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HOLDBYT3 : Hold QEI_CNT by Timer 3
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HOLDCNT : Hold QEI_CNT Control Bit When this bit is set from low to high, the QEI_CNT value is copied into QEI_CNTHLD. This bit may be set by writing 1 to itself through software or Timer0~Timer3 interrupt flag (TISTR.TIF). Note: This bit is automatically cleared after QEI_CNTHLD holds QEI_CNT value.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IDXLAT : Index Latch QEI_CNT Enable Bit\nIf this bit is set to high, the QEI_CNT content will be latched into QEI_CNTILAT at every rising on signal CHX.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IDXRLD_EN : Index Trigger QEI_CNT Reload Enable Bit
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMP_EN : The Compare Function Enable Bit\nThe compare function in QEI controller is to compare the dynamic counting QEPCNT with the compare register QEI_CNTCMP, if QEI_CNT value reaches QEI_CNTCMP, the flag CMPF will be set.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

QEI_EN : Quadrature Encoder Interface Controller Enable Bit
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IDXF : IDX Detected Flag\nWhen the QEI controller detects a rising edge on signal CHX it will set flag IDXF to high.\nNote: This bit is only cleared by writing 1 to itself through software.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPF : Compare-match Flag\nIf the QEI compare function is enabled, the flag is set by hardware while QEI counter up or down counts and reach to the QEI_CNTCMP value.\nNote: This bit is only cleared by writing 1 to itself through software.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OVUNF : QEI Counter Overflow or Underflow Flag\nFlag is set by hardware while QEI_CNT overflows from 0xFFFF_FFFF to 0 in Free-counting mode or from the QEI_MAXCNT value to 0 in compare-counting mode. Similarly, the flag is set wile QEI counter underflows from 0 to 0xFFFF_FFFF or QEI_MAXCNT.\nNote: This bit is only cleared by writing 1 to itself through software.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DIRF : Direction Change Flag\nFlag is set by hardware while QEI counter counting direction is changed, software can clear this bit by writing a one to it.\nNote: This bit is only cleared by writing 1 to itself through software.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DIR : QEI Counter Counting Direction Indication Bit\nNote: This bit is set/reset by hardware according to the phase detection between CHA and CHB.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

QEI_CNTHLD : Quadrature Encoder Pulse Counter Hold Register\nWhen bit HOLDCNT (QEIxCTR[24]) goes from low to high, the QEPCNT value is copied into QEPCNTHLD register.
bits : 0 - 31 (32 bit)
access : read-write

QEI_CNTILAT : Quadrature Encoder Pulse Counter Index Latch Register\nWhen bit IDXF (QEI_STS[18]) is set, the QEPI_CNT value is copied into QEI_CNTILAT register.
bits : 0 - 23 (24 bit)
access : read-write

QEI_CNTCMP : Quadrature Encoder Pulse Counter Compare Register
bits : 0 - 31 (32 bit)
access : read-write