ADDRA0

ADDRA4

ADDRA5

ADDRA6

ADDRA7

ADDRB0

ADDRB1

ADDRB2

ADDRB3

ADDRB4

ADDRB5

ADDRB6

ADDRB7

ADDRA1

ADCR

ADCHISELR

ADSSTR

ADSTPFR

ADIFOVR

ADSPOVFR

ADSPCRA0

ADSPCRA1

ADSPCRA2

ADSPCRA3

ADSPCRA4

ADSPCRA5

ADSPCRA6

ADSPCRA7

ADSPCRB0

ADSPCRB1

ADDRA2

ADSPCRB2

ADSPCRB3

ADSPCRB4

ADSPCRB5

ADSPCRB6

ADSPCRB7

ADITSSELR

ADSMSELR

ADCMPR0

ADCMPR1

ADSR0

ADSR1

ADTCR

ADDRA3

RSLT : A/D Conversion Result\nThis field contains 12-bit conversion result.
bits : 0 - 11 (12 bit)
access : read-only

OVERRUN : Over Run Flag\nIf converted data in RSLT[11:0] has not been read before new conversion result is loaded to this register, OVERRUN is set to 1. It is cleared by hardware after ADDR register is read.
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

VALID : Valid Flag\nThis bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after ADDR register is read.
bits : 17 - 17 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

AD_EN : A/D Converter Enable\nBefore starting the A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit power consumption.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADRESET : ADCA, ADCB A/D Converter control circuits reset\nADRESET bit remains 1 during ADC reset, when ADC reset end, the ADRESET bit is automatically cleared to 0.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADIE0 : Specific SAMPLE A/D ADINT0 Interrupt Enable\nThe A/D converter generates a conversion end ADF0 flag in ADSR1 register upon the end of specific SAMPLE A/D conversion. If ADIE0 bit is set then conversion end interrupt request ADINT0 is generated.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADIE1 : Specific SAMPLE A/D ADINT1 Interrupt Enable\nThe A/D converter generates a conversion end ADF1 flag in ADSR1 register upon the end of specific SAMPLE A/D conversion. If ADIE1 bit is set then conversion end interrupt request ADINT1 is generated.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADIE2 : Specific SAMPLE A/D ADINT2 Interrupt Enable\nThe A/D converter generates a conversion end ADF2 flag in ADSR1 register upon the end of specific SAMPLE A/D conversion. If ADIE2 bit is set then conversion end interrupt request ADINT2 is generated.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADIE3 : Specific SAMPLE A/D ADINT3 Interrupt Enable\nThe A/D converter generates a conversion end ADF3 flag in ADSR1 register upon the end of specific SAMPLE A/D conversion. If ADIE3 bit is set then conversion end interrupt request ADINT3 is generated.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AINA0SEL : A/D Channel AINA[0] Analog Input Selection
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AINB0SEL : A/D Channel AINB[0] Analog Input Selection
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PRESEL : A/D Channel AINA[7] Analog Input Selection
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADST7_0 : A/D SAMPLEA7~0 Software Force to Start ADC Conversion Register
bits : 0 - 7 (8 bit)
access : write-only

Enumeration:

End of enumeration elements list.

ADST15_8 : A/D SAMPLEB7~0 Software Force to Start ADC Conversion Register
bits : 8 - 15 (8 bit)
access : write-only

Enumeration:

End of enumeration elements list.

STPF7_0 : A/D SAMPLEA7~0 Start Conversion Pending Flag \nThis bit remains 1 during pending state, when the respective ADC conversion is started, the STPFx bit is automatically cleared to 0.
bits : 0 - 7 (8 bit)
access : read-only

Enumeration:

End of enumeration elements list.

STPF15_8 : A/D SAMPLEB7~0 Start Conversion Pending Flag \nThis bit remains 1 during pending state, when the respective ADC conversion is started, the STPFx bit is automatically cleared to 0.
bits : 8 - 15 (8 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ADFOV0 : A/D ADINT0 Interrupt flag over run bit It is cleared by write 1.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADFOV1 : A/D ADINT1 Interrupt flag over run bit It is cleared by write 1.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADFOV2 : A/D ADINT2 Interrupt flag over run bit It is cleared by write 1.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADFOV3 : A/D ADINT3 Interrupt flag over run bit It is cleared by write 1.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPOVF7_0 : A/D SAMPLEA7~0 Start Conversion Over Run Flag\nIt is cleared by writing 1.
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPOVF15_8 : A/D SAMPLEB7~0 Start Conversion Over Run Flag\nIt is cleared by writing 1.
bits : 8 - 15 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHSEL : A/D SAMPLEA,B Channel Selection
bits : 0 - 2 (3 bit)
access : read-write

TRGSEL : A/D SAMPLE Start Conversion Trigger Source Selection
bits : 4 - 7 (4 bit)
access : read-write

TRGDLYCNT : A/D SAMPLE Start Conversion Trigger Delay Time
bits : 8 - 15 (8 bit)
access : read-write

TRGDLYDIV : A/D SAMPLE Start Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRGTYPE : A/D SAMPLE Trigger Type Selection
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHSEL : A/D SAMPLEA,B Channel Selection
bits : 0 - 2 (3 bit)
access : read-write

TRGSEL : A/D SAMPLE Start Conversion Trigger Source Selection
bits : 4 - 6 (3 bit)
access : read-write

TRGTYPE : A/D SAMPLEx Trigger Type Selection
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADINT0SEL : A/D ADINT0 Interrupt Trigger Source Selection
bits : 0 - 4 (5 bit)
access : read-write

ADINT1SEL : A/D ADINT1 Interrupt Trigger Source Selection
bits : 8 - 12 (5 bit)
access : read-write

ADINT2SEL : A/D ADINT2 Interrupt Trigger Source Selection
bits : 16 - 19 (4 bit)
access : read-write

ADINT3SEL : A/D ADINT3 Interrupt Trigger Source Selection
bits : 24 - 27 (4 bit)
access : read-write

SIMUSEL0 : A/D SAMPLEA0, SAMPLEB0 Simultaneous Sampling Mode Selection
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SIMUSEL1 : A/D SAMPLEA1, SAMPLEB1 Simultaneous Sampling Mode Selection
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SIMUSEL2 : A/D SAMPLEA2, SAMPLEB2 Simultaneous Sampling Mode Selection
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SIMUSEL3 : A/D SAMPLEA3, SAMPLEB3 Simultaneous Sampling Mode Select ion
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SIMUSEL4 : A/D SAMPLEA4, SAMPLEB4 Simultaneous Sampling Mode Select ion
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SIMUSEL5 : A/D SAMPLEA5, SAMPLEB5 Simultaneous Sampling Mode Selection
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SIMUSEL6 : A/D SAMPLEA6, SAMPLEB6 Simultaneous Sampling Mode Selection
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SIMUSEL7 : A/D SAMPLEA7, SAMPLEB7 Simultaneous Sampling Mode Selection
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCMP_EN : A/D Result Compare Enable\nSet this bit to 1 to enable compare CMPD[11:0] with specified SAMPLE conversion result when converted data is loaded into ADDR register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCMPIE : A/D Result Compare Interrupt Enable\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, ADCMPF bit will be asserted, in the meanwhile, if ADCMPIE is set to 1, a compare interrupt request is generated.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPCOND : Compare Condition\nNote: When the internal counter reaches the value to (CMPMATCNT +1), the CMPF bit will be set.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPSMPL : Compare SAMPLE Selection
bits : 3 - 5 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPMATCNT : Compare Match Count\nWhen the specified A/D SAMPLE analog conversion result matches the compare condition defined by CMPCOND, the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPF bit will be set.
bits : 8 - 11 (4 bit)
access : read-write

CMPD : Comparison Data\nThe 12 bits data is used to compare with the conversion result of specified SAMPLE. Software can use it to monitor the external analog input pin voltage transition without imposing a load on software.
bits : 16 - 27 (12 bit)
access : read-write

VALID7_0 : ADDRA7~0 Data Valid Flag\nIt is a mirror of VALID bit in SAMPLEA A/D result data register ADDRAx
bits : 0 - 7 (8 bit)
access : read-only

VALID15_8 : ADDRB7~0 Data Valid Flag\nIt is a mirror of VALID bit in SAMPLEB A/D result data register ADDRBx
bits : 8 - 15 (8 bit)
access : read-only

OVERRUN7_0 : ADDRA7~0 Over Run Flag\nIt is a mirror to OVERRUN bit in SAMPLEA A/D result data register ADDRAx
bits : 16 - 23 (8 bit)
access : read-only

OVERRUN15_8 : ADDRB7~0 Over Run Flag\nIt is a mirror to OVERRUN bit in SAMPLEB A/D result data register ADDRBx
bits : 24 - 31 (8 bit)
access : read-only

ADF0 : A/D ADINT0 Interrupt Flag\nIt is cleared by writing 1.\nThis bit indicates whether an A/D conversion of specific SAMPLE has been completed.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADF1 : A/D ADINT1 Interrupt Flag\nIt is cleared by writing 1.\nThis bit indicates whether an A/D conversion of specific SAMPLE has been completed.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADF2 : A/D ADINT2 Interrupt Flag\nIt is cleared by writing 1. \nThis bit indicates whether an A/D conversion of specific SAMPLE has been completed.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADF3 : A/D ADINT3 Interrupt Flag\nIt is cleared by writing 1.\nThis bit indicates whether an A/D conversion of specific SAMPLE has been completed
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCMPO0 : ADC Compare 0 Output Status Bit The 12 bits compare0 data (ADCMPR0[27:16]) is used to compare with conversion result of specified SAMPLE. Software can use it to monitor the external analog input pin voltage status.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCMPO1 : ADC Compare 1 Output Status Bit The 12 bits compare1 data (ADCMPR1[27:16]) is used to compare with conversion result of specified SAMPLE. Software can use it to monitor the external analog input pin voltage status.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCMPF0 : ADC Compare 0 Flag\nWhen the specific SAMPLE A/D conversion result meets setting condition in ADCMPR0 then this bit is set to 1. And it is cleared by write 1.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCMPF1 : ADC Compare 1 Flag\nWhen the specific SAMPLE A/D conversion result meets setting condition in ADCMPR1 then this bit is set to 1. And it is cleared by write 1.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUSYA : BUSY/IDLE\nIt is read only.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHANNELA : Current Conversion Channel
bits : 12 - 14 (3 bit)
access : read-write

BUSYB : BUSY/IDLE\nIt is read only.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHANNELB : Current Conversion Channel
bits : 20 - 22 (3 bit)
access : read-write

AADFOV : All A/D Interrupt Flag Over Run Bits Check \nThis bit will keep 1 when any ADFOVx Flag is equal to 1.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ASPOVF : All A/D SAMPLE Start Conversion Over Run Flags Check\nThis bit will keep 1 when any SPOVFx Flag is equal to 1.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AVALID : All SAMPLE A/D Result Data Register ADDR Data Valid Flag Check\nThis bit will keep 1 when any VALIDx Flag is equal to 1.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AOVERRUN : All SAMPLE A/D Result Data Register Over Run Flags Check \nThis bit will keep 1 when any OVERRUNx Flag is equal to 1.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.