\n
address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x44 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
ADC Data Register
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RESULT : A/D Conversion Result\nThis field contains conversion result of ADC.
bits : 0 - 9 (10 bit)
access : read-only
OV : Over Run Flag\nIf converted data in RESULT[9:0] has not been read before the new conversion result is loaded to this register, OV is set to 1. It is cleared by hardware after the ADC_DAT register is read.
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Data in RESULT[9:0] is recent conversion result
#1 : 1
Data in RESULT[9:0] overwrote
End of enumeration elements list.
VALID : Valid Flag\nThis bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADC_DAT register is read.
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
Data in RESULT[9:0] bits not valid
#1 : 1
Data in RESULT[9:0] bits valid
End of enumeration elements list.
ADC Control Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCEN : A/D Converter Enable\nNote: Before starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit to save power consumption.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
A/D Converter Disabled
#1 : 1
A/D Converter Enabled
End of enumeration elements list.
ADCIEN : A/D Interrupt Enable\nA/D conversion end interrupt request is generated if ADCIEN bit is set to 1.\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
A/D interrupt function Disabled
#1 : 1
A/D interrupt function Enabled
End of enumeration elements list.
HWTRGSEL : Hardware Trigger Source\nNote: Software should disable HWTRGEN and SWTRG before change HWTRGSEL.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
A/D conversion is started by external STADC pin
#11 : 3
A/D conversion is started by PWM trigger
End of enumeration elements list.
HWTRGCOND : External Trigger Condition\nThis bit decides whether the external pin STADC trigger event is falling or raising edge. The signal must be kept at stable state at least 4 PCLKs at high and low state for edge trigger.\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling edge
#1 : 1
Raising edge
End of enumeration elements list.
HWTRGEN : External Trigger Enable\nEnable or disable triggering of A/D conversion by external STADC pin. If external trigger is enabled, the SWTRG bit can be set to 1 by the selected hardware trigger source.\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
External trigger Disabled
#1 : 1
External trigger Enabled
End of enumeration elements list.
SWTRG : A/D Conversion Start\nSWTRG bit can be set to 1 from two sources: software and external pin STADC. SWTRG will be cleared to 0 by hardware automatically after conversion complete.\n
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Conversion stopped and A/D converter entered idle state
#1 : 1
Conversion start
End of enumeration elements list.
VREFSEL : Reference Voltage Selection Signal\n
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Connect VDD5V to internal reference
#1 : 1
Connect VREF (AIN0) pin to internal reference
End of enumeration elements list.
ADC Channel Enable Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN0 : Analog Input Channel 0 Enable\nNote: If software enables more than one channel, the channel with the smallest number will be selected and the other enabled channels will be ignored.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel 0 Disabled
#1 : 1
Channel 0 Enabled
End of enumeration elements list.
CHEN1 : Analog Input Channel 1 Enable\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel 1 Disabled
#1 : 1
Channel 1 Enabled
End of enumeration elements list.
CHEN2 : Analog Input Channel 2 Enable\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel 2 Disabled
#1 : 1
Channel 2 Enabled
End of enumeration elements list.
CHEN3 : Analog Input Channel 3 Enable\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel 3 Disabled
#1 : 1
Channel 3 Enabled
End of enumeration elements list.
CHEN4 : Analog Input Channel 4 Enable\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel 4 Disabled
#1 : 1
Channel 4 Enabled
End of enumeration elements list.
CHEN5 : Analog Input Channel 5 Enable\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel 5 Disabled
#1 : 1
Channel 5 Enabled
End of enumeration elements list.
CHEN6 : Analog Input Channel 6 Enable\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel 6 Disabled
#1 : 1
Channel 6 Enabled
End of enumeration elements list.
CHEN7 : Analog Input Channel 7 Enable\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel 7 Disabled
#1 : 1
Channel 7 Enabled
End of enumeration elements list.
CH7SEL : Analog Input Channel 7 Selection\nNote: When software selects the band-gap voltage as the analog input source of ADC channel 7, the ADC clock rate needs to be limited to lower than 300 kHz.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
External analog input
#1 : 1
Internal band-gap voltage (VBG)
End of enumeration elements list.
CHEN8 : Analog Input Channel 8 Enable\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CHEN9 : Analog Input Channel 9 Enable\n
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CHEN10 : Analog Input Channel 10 Enable\n
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CHEN11 : Analog Input Channel 11 Enable\n
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BGEN : Band-Gap Voltage Measurement\nNote: User can set BGEN high to use ADC to measure Band-Gap voltage directly to instead of enabling PRESET and CHEN7.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
ADC Compare Register 0
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCMPEN : Compare Enable\nSet 1 to this bit to enable comparing CMPDAT[9:0] with specified channel conversion results when converted data is loaded into the ADC_DAT register.\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare function Disabled
#1 : 1
Compare function Enabled
End of enumeration elements list.
ADCMPIE : Compare Interrupt Enable\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMCNT, ADCMPFx bit will be asserted, in the meanwhile, if CMPCOND is set to 1, a compare interrupt request is generated.\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare function interrupt Disabled
#1 : 1
Compare function interrupt Enabled
End of enumeration elements list.
CMPCOND : Compare Condition\nNote: When the internal counter reaches the value to (CMPMCNT +1), the ADCMPFx bit will be set.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Set the compare condition as that when a 10-bit A/D conversion result is less than the 10-bit CMPDAT (ADCMPRx[25:16]), the internal match counter will increase one
#1 : 1
Set the compare condition as that when a 10-bit A/D conversion result is greater or equal to the 10-bit CMPDAT (ADCMPRx[25:16]), the internal match counter will increase one
End of enumeration elements list.
CMPCH : Compare Channel Selection\n
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
#0000 : 0
Channel 0 conversion result is selected to be compared
#0001 : 1
Channel 1 conversion result is selected to be compared
#0010 : 2
Channel 2 conversion result is selected to be compared
#0011 : 3
Channel 3 conversion result is selected to be compared
#0100 : 4
Channel 4 conversion result is selected to be compared
#0101 : 5
Channel 5 conversion result is selected to be compared
#0110 : 6
Channel 6 conversion result is selected to be compared
#0111 : 7
Channel 7 conversion result is selected to be compared
#1000 : 8
Channel 8 conversion result is selected to be compared
#1001 : 9
Channel 9 conversion result is selected to be compared
#1010 : 10
Channel 10 conversion result is selected to be compared
#1011 : 11
Channel 11 conversion result is selected to be compared
#1100 : 12
band-gap voltage result is selected to be compared
End of enumeration elements list.
CMPMCNT : Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2], the internal match counter will increase 1. When the internal counter reaches the value to (CMPMCNT +1), the ADCMPFx bit will be set.
bits : 8 - 11 (4 bit)
access : read-write
CMPDAT : Comparison Data\nThe 10-bit data is used to compare with conversion result of specified channel.
bits : 16 - 25 (10 bit)
access : read-write
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Status Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADIF : A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion. ADIF is set to 1 When A/D conversion ends.\nSoftware can write 1 to clear this bit to zero.
bits : 0 - 0 (1 bit)
access : read-write
ADCMPF0 : Compare Flag 0\nWhen the selected channel A/D conversion result meets the setting condition in ADC_CMP0, this bit is set to 1. Software can write 1 to clear this bit to zero.\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Conversion result in ADC_DAT does not meet the ADC_CMP0 setting
#1 : 1
Conversion result in ADC_DAT meets the ADC_CMP0 setting
End of enumeration elements list.
ADCMPF1 : Compare Flag 1\nWhen the selected channel A/D conversion result meets the setting condition in ADC_CMP1, this bit is set to 1. Software can write 1 to clear this bit to zero.\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Conversion result in ADC_DAT does not meet the ADC_CMP1 setting
#1 : 1
Conversion result in ADC_DAT meets the ADC_CMP1 setting
End of enumeration elements list.
BUSY : BUSY/IDLE (Read Only)\nThis bit is mirror of as SWTRG bit in ADC_CTL\n
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
A/D converter is in idle state
#1 : 1
A/D converter is busy at conversion
End of enumeration elements list.
CHANNEL : Current Conversion Channel (Read Only)\n
bits : 4 - 6 (3 bit)
access : read-only
VALID : Data Valid Flag (Read Only)\nIt is a mirror of VALID bit in ADC_DAT register.
bits : 8 - 8 (1 bit)
access : read-only
OV : OV Flag (Read Only)\nIt is a mirror to OV bit in ADC_DAT register.
bits : 16 - 16 (1 bit)
access : read-only
ADC Trigger Delay Control Register
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DELAY : PWM Trigger Delay Timer\nSet this field will delay ADC start conversion time after PWM trigger.\nPWM trigger delay time is (4 * DELAY) * system clock.
bits : 0 - 7 (8 bit)
access : read-write
ADC Sampling Time Counter Register
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXTSMPT : ADC Sampling Counter\nADC sampling counters are 6 ADC clock is suggestion.
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
6 ADC Clock
#0001 : 1
7 ADC Clock
#0010 : 2
8 ADC Clock
#0011 : 3
10 ADC Clock
#0100 : 4
14 ADC Clock
#0101 : 5
22 ADC Clock
#0110 : 6
38 ADC Clock
#0111 : 7
70 ADC Clock
#1000 : 8
1346 ADC Clock
#1001 : 9
262 ADC Clock
#1010 : 10
518 ADC Clock
#1011 : 11
1030 ADC Clock
#1100 : 12
1030 ADC Clock
#1101 : 13
1030 ADC Clock
#1110 : 14
1030 ADC Clock
#1111 : 15
1030 ADC Clock
End of enumeration elements list.
ADC PWM Sequential Mode Control Register
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEQEN : ADC Sequential Mode Enable\nWhen ADC sequential mode is enabled, two of three ADC channels from 0 to 2 will automatically convert analog data in the sequence of channel [0, 1] or channel[1, 2] or channel[0, 2] defined by SEQ_MODE[1:0].\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
ADC sequential mode Disabled
#1 : 1
ADC sequential mode Enabled
End of enumeration elements list.
SEQTYPE : ADC Sequential Mode Type\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
ADC delay time is only inserted before the first conversion. The second conversion starts immediately after the first conversion is completed. (for 2/3-shunt type)
#1 : 1
ADC delay time is inserted before each conversion. (for 1-shunt type)
End of enumeration elements list.
MODESEL : ADC Sequential Mode Selection\n
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Issue ADC_INT after Channel 0 then Channel 1 conversion finishes when SEQEN =1
#01 : 1
Issue ADC_INT after Channel 1 then Channel 2 conversion finishes when SEQEN =1
#10 : 2
Issue ADC_INT after Channel 0 then Channel 2 conversion finishes when SEQEN =1
#11 : 3
Reserved
End of enumeration elements list.
TRG1TYPE : ADC Sequential Mode Trigger1 Type\n
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Rising of the selected PWM
#01 : 1
Center of the selected PWM
#10 : 2
Falling of the selected PWM
#11 : 3
Period of the selected PWM
End of enumeration elements list.
TRG1SRC : ADC Sequential Mode Trigger1 Source\n
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 0
PWM0
#01 : 1
PWM2
#10 : 2
PWM4
#11 : 3
Reserved
End of enumeration elements list.
TRG2TYPE : ADC Sequential Mode Trigger2 Type\n
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
Rising of the selected PWM
#01 : 1
Center of the selected PWM
#10 : 2
Falling of the selected PWM
#11 : 3
Period of the selected PWM
End of enumeration elements list.
TRG2SRC : ADC Sequential Mode Trigger2 Source\n
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 0
PWM0
#01 : 1
PWM2
#10 : 2
PWM4
#11 : 3
Reserved
End of enumeration elements list.
ADC PWM Sequential Mode Result Register 0
address_offset : 0x50 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RESULT : A/D PWM Sequential Mode Conversion Result\nThis field contains conversion result of ADC.
bits : 0 - 9 (10 bit)
access : read-only
OV : Over Run Flag\nIf converted data in RESULT [9:0] has not been read before the new conversion result is loaded to this register, OV is set to 1. It is cleared by hardware after the ADC_DAT register is read.
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Data in RESULT [9:0] is recent conversion result
#1 : 1
Data in RESULT [9:0] overwritten
End of enumeration elements list.
VALID : Valid Flag\nThis bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADC_DAT register is read.
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
Data in RESULT [9:0] bits not valid
#1 : 1
Data in RESULT. ADC_TRGDLY [9:0] bits valid
End of enumeration elements list.
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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