\n
address_offset : 0x0 Bytes (0x0)
size : 0x3C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x54 Bytes (0x0)
size : 0x34 byte (0x0)
mem_usage : registers
protection : not protected
PWM Pre-scale Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CP01 : Clock Prescaler 0 for PWM Counter 0 and 1
Clock input is divided by (CP01 + 1) before it is fed to the corresponding PWM counter.
bits : 0 - 7 (8 bit)
access : read-write
CP23 : Clock Prescaler 2 for PWM Counter 2 and 3\nClock input is divided by (CP23 + 1) before it is fed to the corresponding PWM counter.
bits : 8 - 15 (8 bit)
access : read-write
CP45 : Clock Prescaler 4 for PWM Counter 4 and 5\nClock input is divided by (CP45 + 1) before it is fed to the corresponding PWM counter.
bits : 16 - 23 (8 bit)
access : read-write
PWM Counter Register 1
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Counter Register 2
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Counter Register 3
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Counter Register 4
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Counter Register 5
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Comparator Register 0
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMRn : PWM Comparator Bits\nNote: Any write to CMRn will take effect in next PWM cycle.
bits : 0 - 15 (16 bit)
access : read-write
PWM Comparator Register 1
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Comparator Register 2
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Comparator Register 3
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Comparator Register 4
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Comparator Register 5
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Clock Select Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSR0 : Timer 0 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CSR5.)
bits : 0 - 2 (3 bit)
access : read-write
CSR1 : Timer 1 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CSR5.)
bits : 4 - 6 (3 bit)
access : read-write
CSR2 : Timer 2 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CSR5.)
bits : 8 - 10 (3 bit)
access : read-write
CSR3 : Timer 3 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CSR5.)
bits : 12 - 14 (3 bit)
access : read-write
CSR4 : Timer 4 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CSR5.)
bits : 16 - 18 (3 bit)
access : read-write
CSR5 : Timer 5 Clock Source Selection\nSelect clock input for PWM timer.
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
#000 : 0
Input Clock Divided by 2
#001 : 1
Input Clock Divided by 4
#010 : 2
Input Clock Divided by 8
#011 : 3
Input Clock Divided by 16
#100 : 4
Input Clock Divided by 1
End of enumeration elements list.
PWM Interrupt Enable Control Register
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWMPIE0 : PWM Channel 0 Period Interrupt Enable Control
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PWMPIE1 : PWM Channel 1 Period Interrupt Enable Control
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PWMPIE2 : PWM Channel 2 Period Interrupt Enable Control
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PWMPIE3 : PWM Channel 3 Period Interrupt Enable Control
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PWMPIE4 : PWM Channel 4 Period Interrupt Enable Control
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PWMPIE5 : PWM Channel 5 Period Interrupt Enable Control
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PWMDIE0 : PWM Channel 0 Duty Interrupt Enable Control
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PWMDIE1 : PWM Channel 1 Duty Interrupt Enable Control
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PWMDIE2 : PWM Channel 2 Duty Interrupt Enable Control
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PWMDIE3 : PWM Channel 3 Duty Interrupt Enable Control
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PWMDIE4 : PWM Channel 4 Duty Interrupt Enable Control
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PWMDIE5 : PWM Channel 5 Duty Interrupt Enable Control
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BRKIE : Fault Brake0 and 1 Interrupt Enable Control
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabling flags BKF0 and BKF1 to trigger PWM interrupt
#1 : 1
Enabling flags BKF0 and BKF1 can trigger PWM interrupt
End of enumeration elements list.
INT_TYPE : PWM Interrupt Type Selection Bit\nNote: This bit is effective when PWM in central align mode only.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMPIFn will be set if PWM counter underflows
#1 : 1
PWMPIFn will be set if PWM counter matches CNRn register
End of enumeration elements list.
PWM Interrupt Indication Register
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWMPIF0 : PWM channel 0 Period Interrupt Flag\nFlag is set by hardware when PWM0 down counter reaches zero. \nNote: Software can write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write
PWMPIF1 : PWM channel 1 Period Interrupt Flag\nFlag is set by hardware when PWM1 down counter reaches zero. \nNote: Software can write 1 to clear this bit.
bits : 1 - 1 (1 bit)
access : read-write
PWMPIF2 : PWM channel 2 Period Interrupt Flag\nFlag is set by hardware when PWM2 down counter reaches zero. \nNote: Software can write 1 to clear this bit.
bits : 2 - 2 (1 bit)
access : read-write
PWMPIF3 : PWM channel 3 Period Interrupt Flag\nFlag is set by hardware when PWM3 down counter reaches zero. \nNote: Software can write 1 to clear this bit.
bits : 3 - 3 (1 bit)
access : read-write
PWMPIF4 : PWM channel 4 Period Interrupt Flag\nFlag is set by hardware when PWM4 down counter reaches zero. \nNote: Software can write 1 to clear this bit.
bits : 4 - 4 (1 bit)
access : read-write
PWMPIF5 : PWM channel 5 Period Interrupt Flag\nFlag is set by hardware when PWM5 down counter reaches zero. \nNote: Software can write 1 to clear this bit.
bits : 5 - 5 (1 bit)
access : read-write
PWMDIF0 : PWM channel 0 Duty Interrupt Flag\nFlag is set by hardware when a channel 0 PWM counter reaches CMR0 in down-count direction. \nNote: Software can write 1 to clear this bit.
bits : 8 - 8 (1 bit)
access : read-write
PWMDIF1 : PWM channel 1 Duty Interrupt Flag\nFlag is set by hardware when a channel 1 PWM counter reaches CMR1 in down-count direction. \nNote: Software can write 1 to clear this bit.
bits : 9 - 9 (1 bit)
access : read-write
PWMDIF2 : PWM channel 2 Duty Interrupt Flag\nFlag is set by hardware when a channel 2 PWM counter reaches CMR2 in down-count direction. \nNote: Software can write 1 to clear this bit.
bits : 10 - 10 (1 bit)
access : read-write
PWMDIF3 : PWM channel 3 Duty Interrupt Flag\nFlag is set by hardware when a channel 3 PWM counter reaches CMR3 in down-count direction. \nNote: Software can write 1 to clear this bit.
bits : 11 - 11 (1 bit)
access : read-write
PWMDIF4 : PWM channel 4 Duty Interrupt Flag\nFlag is set by hardware when a channel 4 PWM counter reaches CMR4 in down-count direction. \nNote: Software can write 1 to clear this bit.
bits : 12 - 12 (1 bit)
access : read-write
PWMDIF5 : PWM channel 5 Duty Interrupt Flag\nFlag is set by hardware when a channel 5 PWM counter reaches CMR5 in down-count direction. \nNote: Software can write 1 to clear this bit.
bits : 13 - 13 (1 bit)
access : read-write
BKF0 : PWM Brake0 Flag\nNote: Software can write 1 to clear this bit.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Brake does not recognize a falling signal at BKP0
#1 : 1
When PWM Brake detects a falling signal at pin BKP0, this flag will be set to high
End of enumeration elements list.
BKF1 : PWM Brake1 Flag\nNote: Software can write 1 to clear this bit.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Brake does not recognize a falling signal at BKP1
#1 : 1
When PWM Brake detects a falling signal at pin BKP1, this flag will be set to high
End of enumeration elements list.
PWM Output Enable for Channel 0~5
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM0 : PWM Channel 0 Output Enable Control\nNote: The corresponding GPIO pin must be switched to PWM function.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel 0 output to pin Disabled
#1 : 1
PWM channel 0 output to pin Enabled
End of enumeration elements list.
PWM1 : PWM Channel 1 Output Enable Control\nNote: The corresponding GPIO pin must be switched to PWM function.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel 1 output to pin Disabled
#1 : 1
PWM channel 1 output to pin Enabled
End of enumeration elements list.
PWM2 : PWM Channel 2 Output Enable Control\nNote: The corresponding GPIO pin must be switched to PWM function.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel 2 output to pin Disabled
#1 : 1
PWM channel 2 output to pin Enabled
End of enumeration elements list.
PWM3 : PWM Channel 3 Output Enable Control\nNote: The corresponding GPIO pin must be switched to PWM function.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel 3 output to pin Disabled
#1 : 1
PWM channel 3 output to pin Enabled
End of enumeration elements list.
PWM4 : PWM Channel 4 Output Enable Control\nNote: The corresponding GPIO pin must be switched to PWM function.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel 4 output to pin Disabled
#1 : 1
PWM channel 4 output to pin Enabled
End of enumeration elements list.
PWM5 : PWM Channel 5 Output Enable Control\nNote: The corresponding GPIO pin must be switched to PWM function.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel 5 output to pin Disabled
#1 : 1
PWM channel 5 output to pin Enabled
End of enumeration elements list.
PWM Fault Brake Control Register
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKEN0 : Enable BKP0 Pin Trigger Fault Brake Function 0
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabling BKP0 pin can trigger brake function 0 (EINT0 or CPO1)
#1 : 1
Enabling a falling at BKP0 pin can trigger brake function 0
End of enumeration elements list.
BKEN1 : Enable BKP1 Pin Trigger Fault Brake Function 1
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabling BKP1 pin can trigger brake function 1 (EINT1 or CPO0)
#1 : 1
Enabling a falling at BKP1 pin can trigger brake function 1
End of enumeration elements list.
CPO0BKEN : BKP1 Fault Brake Function Source Selection
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
EINT1 as one brake source in BKP1
#1 : 1
CPO0 as one brake source in BKP1
End of enumeration elements list.
CPO1BKEN : BKP0 Fault Brake Function Source Selection
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
EINT0 as one brake source in BKP0
#1 : 1
CPO1 as one brake source in BKP0
End of enumeration elements list.
BKF : PWM Fault Brake Event Flag (write 1 clear)\nSoftware can write 1 to clear this bit and must clear this bit before restart PWM counter.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output initial state when fault brake conditions asserted
#1 : 1
PWM output fault brake state when fault brake conditions asserted
End of enumeration elements list.
PWMBKO0 : PWM Channel 0 Brake Output Select Bit
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output low when fault brake conditions asserted
#1 : 1
PWM output high when fault brake conditions asserted
End of enumeration elements list.
PWMBKO1 : PWM Channel 1 Brake Output Select Bit
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output low when fault brake conditions asserted
#1 : 1
PWM output high when fault brake conditions asserted
End of enumeration elements list.
PWMBKO2 : PWM Channel 2 Brake Output Select Bit
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output low when fault brake conditions asserted
#1 : 1
PWM output high when fault brake conditions asserted
End of enumeration elements list.
PWMBKO3 : PWM Channel 3 Brake Output Select Bit
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output low when fault brake conditions asserted
#1 : 1
PWM output high when fault brake conditions asserted
End of enumeration elements list.
PWMBKO4 : PWM Channel 4 Brake Output Select Bit
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output low when fault brake conditions asserted
#1 : 1
PWM output high when fault brake conditions asserted
End of enumeration elements list.
PWMBKO5 : PWM Channel 5 Brake Output Select Bit
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output low when fault brake conditions asserted
#1 : 1
PWM output high when fault brake conditions asserted
End of enumeration elements list.
D6BKO6 : D6 Brake Output Select Bit
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
D6 output low when fault brake conditions asserted
#1 : 1
D6 output high when fault brake conditions asserted
End of enumeration elements list.
D7BKO7 : D7 Brake Output Select Bit
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
D7 output low when fault brake conditions asserted
#1 : 1
D7 output high when fault brake conditions asserted
End of enumeration elements list.
PWM Dead-zone Interval Register
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DZI01 : Dead-zone Interval Register for Pair of Channel0 and Channel1 (PWM0 and PWM1 pair).\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding CSR bits.
bits : 0 - 7 (8 bit)
access : read-write
DZI23 : Dead-zone Interval Register for Pair of Channel2 and Channel3 (PWM2 and PWM3 pair).\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding CSR bits.
bits : 8 - 15 (8 bit)
access : read-write
DZI45 : Dead-zone Interval Register for Pair of Channel4 and Channel5 (PWM4 and PWM5 pair).\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding CSR bits.
bits : 16 - 23 (8 bit)
access : read-write
PWM Trigger Control Register 0
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CM0TRGREN : Enable PWM trigger ADC function while Channel0's counter matching CMR0 in up-count direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CNT0TRGEN : Enable PWM trigger ADC function while Channel0's counter matching CNR0\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CM0TRGFEN : Enable PWM trigger ADC function while Channel0's counter matching CMR0 in down-count direction\nNote: This bit is valid for both center aligned mode and edged aligned mode.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
P0TRGEN : Enable PWM trigger ADC function while Channel0's counter matching 0\nNote: This bit is valid for both center aligned mode and edged aligned mode.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CM1TRGREN : Enable PWM trigger ADC function while Channel1's counter matching CMR1 in up-count direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CNT1TRGEN : Enable PWM trigger ADC function while Channel1's counter matching CNR1\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CM1TRGFEN : Enable PWM trigger ADC function while Channel1's counter matching CMR1 in down-count direction\nNote: This bit is valid for both center aligned mode and edged aligned mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
P1TRGEN : Enable PWM trigger ADC function while Channel1's counter matching 0 \nNote: This bit is valid for both center aligned mode and edged aligned mode.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CM2TRGREN : Enable PWM trigger ADC function while Channel2's counter matching CMR2 in up-count direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CNT2TRGEN : Enable PWM trigger ADC function while Channel2's counter matching CNR2\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CM2TRGFEN : Enable PWM trigger ADC function while Channel2's counter matching CMR2 in down-count direction\nNote: This bit is valid for both center aligned mode and edged aligned mode.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
P2TRGEN : Enable PWM trigger ADC function while Channel2's counter matching 0\nNote: This bit is valid for both center aligned mode and edged aligned mode.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CM3TRGREN : Enable PWM trigger ADC function while Channel3's counter matching CMR3 in up-count direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CNT3TRGEN : Enable PWM trigger ADC function while Channel3's counter matching CNR3\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CM3TRGFEN : Enable PWM trigger ADC function while Channel3's counter matching CMR3 in down-count direction\nNote: This bit is valid for both center aligned mode and edged aligned mode.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
P3TRGEN : Enable PWM trigger ADC function while Channel3's counter matching 0\nNote: This bit is valid for both center aligned mode and edged aligned mode.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PWM Trigger Control Register 1
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CM4TRGREN : Enable PWM trigger ADC function while Channel4's counter matching CMR4 in up-count direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CNT4TRGEN : Enable PWM trigger ADC function while Channel4's counter matching CNR4\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CM4TRGFEN : Enable PWM trigger ADC function while Channel4's counter matching CMR4 in down-count direction\nNote: This bit is valid for both center aligned mode and edged aligned mode.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
P4TRGEN : Enable PWM trigger ADC function while Channel4's counter matching 0\nNote: This bit is valid for both center aligned mode and edged aligned mode.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CM5TRGREN : Enable PWM trigger ADC function while Channel5's counter matching CMR5 in up-count direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CNT5TRGEN : Enable PWM trigger ADC function while Channel5's counter matching CNR5\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CM5TRGFEN : Enable PWM trigger ADC function while Channel5's counter matching CMR5 in down-count direction\nNote: This bit is valid for both center aligned mode and edged aligned mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
P5TRGEN : Enable PWM trigger ADC function while Channel5's counter matching 0\nNote: This bit is valid for both center aligned mode and edged aligned mode.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PWM Trigger Status Register 0
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMR0FLAG_R : ADC trigger flag by counting up to CMR\nNote: Software can write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write
CNT0FLAG : ADC trigger flag by counting to CNR
Note: Software can write 1 to clear this bit.
bits : 1 - 1 (1 bit)
access : read-write
CMR0FLAG_F : ADC trigger flag by counting down to CMR\nNote: Software can write 1 to clear this bit.
bits : 2 - 2 (1 bit)
access : read-write
PERID0FLAG : ADC trigger flag by period \nNote: Software can write 1 to clear this bit.
bits : 3 - 3 (1 bit)
access : read-write
CMR1FLAG_R : ADC trigger flag by counting up to CMR\nNote: Software can write 1 to clear this bit.
bits : 8 - 8 (1 bit)
access : read-write
CNT1FLAG : ADC trigger flag by counting to CNR
Note: Software can write 1 to clear this bit.
bits : 9 - 9 (1 bit)
access : read-write
CMR1FLAG_F : ADC trigger flag by counting down to CMR\nNote: Software can write 1 to clear this bit.
bits : 10 - 10 (1 bit)
access : read-write
PERID1FLAG : ADC trigger flag by period \nNote: Software can write 1 to clear this bit.
bits : 11 - 11 (1 bit)
access : read-write
CMR2FLAG_R : ADC trigger flag by counting up to CMR \nNote: Software can write 1 to clear this bit.
bits : 16 - 16 (1 bit)
access : read-write
CNT2FLAG : ADC trigger flag by counting to CNR
Note: Software can write 1 to clear this bit.
bits : 17 - 17 (1 bit)
access : read-write
CMR2FLAG_F : ADC trigger flag by counting down to CMR\nNote: Software can write 1 to clear this bit.
bits : 18 - 18 (1 bit)
access : read-write
PERID2FLAG : ADC trigger flag by period \nNote: Software can write 1 to clear this bit.
bits : 19 - 19 (1 bit)
access : read-write
CMR3FLAG_R : When counter counting up to CMR, this bit will be set for trigger ADC\nNote: Software can write 1 to clear this bit.
bits : 24 - 24 (1 bit)
access : read-write
CNT3FLAG : When counter counting to CNR, this bit will be set for trigger ADC\nNote: Software can write 1 to clear this bit.
bits : 25 - 25 (1 bit)
access : read-write
CMR3FLAG_F : When counter counting down to CMR, this bit will be set for trigger ADC\nNote: Software can write 1 to clear this bit.
bits : 26 - 26 (1 bit)
access : read-write
PERID3FLAG : When counter counting to period, this bit will be set for trigger ADC \nNote: Software can write 1 to clear this bit.
bits : 27 - 27 (1 bit)
access : read-write
PWM Trigger Status Register 1
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMR4FLAG_R : ADC trigger flag by counting up to CMR\nNote: Software can write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write
CNT4FLAG : ADC trigger flag by counting to CNR\nNote: Software can write 1 to clear this bit.
bits : 1 - 1 (1 bit)
access : read-write
CMR4FLAG_F : ADC trigger flag by counting down to CMR\nNote: Software can write 1 to clear this bit.
bits : 2 - 2 (1 bit)
access : read-write
PERID4FLAG : ADC trigger flag by period \nNote: Software can write 1 to clear this bit.
bits : 3 - 3 (1 bit)
access : read-write
CMR5FLAG_R : ADC trigger flag by counting up to CMR\nNote: Software can write 1 to clear this bit.
bits : 8 - 8 (1 bit)
access : read-write
CNT5FLAG : ADC trigger flag by counting to CNR\nNote: Software can write 1 to clear this bit.
bits : 9 - 9 (1 bit)
access : read-write
CMR5FLAG_F : ADC trigger flag by counting down to CMR\nNote: Software can write 1 to clear this bit.
bits : 10 - 10 (1 bit)
access : read-write
PERID5FLAG : ADC trigger flag by period \nNote: Software can write 1 to clear this bit.
bits : 11 - 11 (1 bit)
access : read-write
Phase Changed Register
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0 : D0: when PWM0 is zero, channel 0's output waveform is D0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output low
#1 : 1
Output high
End of enumeration elements list.
D1 : D1: when PWM1 is zero, channel 1's output waveform is D1.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output low
#1 : 1
Output high
End of enumeration elements list.
D2 : D2: when PWM2 is zero, channel 2's output waveform is D2.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output low
#1 : 1
Output high
End of enumeration elements list.
D3 : D3: when PWM3 is zero, channel 3's output waveform is D3.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output low
#1 : 1
Output high
End of enumeration elements list.
D4 : D4: when PWM4 is zero, channel 4's output waveform is D4.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output low
#1 : 1
Output high
End of enumeration elements list.
D5 : D5: when PWM5 is zero, channel 5's output waveform is D5.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output low
#1 : 1
Output high
End of enumeration elements list.
D6 : D6: when MASK6 is 1, channel 6's output waveform is D6.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output low
#1 : 1
Output high
End of enumeration elements list.
D7 : D7: when MASK1 is 1, channel 7's output waveform is D7.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output low
#1 : 1
Output high
End of enumeration elements list.
PWM0 : PWM Channel 0 Output Enable Control
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output the original channel 0 waveform
#1 : 1
Output D0 specified in bit 0 of PHCHG register
End of enumeration elements list.
PWM1 : PWM channel 1 output enable control.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output the original channel 1 waveform
#1 : 1
Output D1 specified in bit 1 of PHCHG register
End of enumeration elements list.
PWM2 : PWM channel 2 output enable control.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output the original channel 2 waveform
#1 : 1
Output D2 specified in bit 2 of PHCHG register
End of enumeration elements list.
PWM3 : PWM channel 3 output enable control.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output the original channel 3 waveform
#1 : 1
Output D3 specified in bit 3 of PHCHG register
End of enumeration elements list.
PWM4 : PWM channel 4 output enable control.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output the original channel 4 waveform
#1 : 1
Output D4 specified in bit 4 of PHCHG register
End of enumeration elements list.
PWM5 : PWM channel 5 output enable control.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output the original channel 5 waveform
#1 : 1
Output D5 specified in bit 5 of PHCHG register
End of enumeration elements list.
ACCNT0 : Hardware auto clear CE0 when ACMP0 trigger it.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enabled
#1 : 1
Disabled
End of enumeration elements list.
ACCNT1 : Hardware auto clear CE1 when ACMP1 trigger it.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enabled
#1 : 1
Disabled
End of enumeration elements list.
CH01TOFF1 : Setting this bit will Force PWM0 to output low lasting for at most one period cycle as long as ACMP1 trigger it this feature is usually in step motor application.
Note: only for PWM0,PWM1,PWM2,PWM3.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CH11TOFF1 : Setting this bit will Force PWM1 to output low lasting for at most one period cycle as long as ACMP1 trigger it this feature is usually in step motor application.
Note: Only for PWM0, PWM1, PWM2, PWM3.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CH21TOFF1 : Setting this bit will Force PWM2 to output low lasting for at most one period cycle as long as ACMP1 trigger it this feature is usually in step motor application.
Note: Only for PWM0, PWM1, PWM2, PWM3.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CH31TOFF1 : Setting this bit will Force PWM3 to output low lasting for at most one period cycle as long as ACMP1 trigger it this feature is usually in step motor application.
Note: Only for PWM0, PWM1, PWM2, PWM3.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CMP1SEL : CMP1SEL\nSelect the positive input source of ACMP1.
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 0
Select P3.1 as the input of ACMP1
#01 : 1
Select P3.2 as the input of ACMP1
#10 : 2
Select P3.3 as the input of ACMP1
#11 : 3
Select P3.4 as the input of ACMP1
End of enumeration elements list.
T1 : Timer1 Trigger PWM Function Enable Control\nWhen this bit is set, timer1 time-out event will update PHCHG with PHCHG_NXT register.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CE1 : ACMP1 Trigger Function Enable Control\nNote: This bit will be auto cleared when ACMP1 trigger PWM if ACCNT1 is set.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CH01TOFF0 : Setting this bit will Force PWM0 to output low lasting for at most one period cycle as long as ACMP0 trigger it this feature is usually in step motor application.
Note: Only for PWM0, PWM1, PWM2, PWM3.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CH11TOFF0 : Setting this bit will Force PWM1 to output low lasting for at most one period cycle as long as ACMP0 trigger it this feature is usually in step motor application.
Note: Only for PWM0, PWM1, PWM2, PWM3.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CH21TOFF0 : Setting this bit will Force PWM2 to output low lasting for at most one period cycle as long as ACMP0 trigger it this feature is usually in step motor application
Note: Only for PWM0, PWM1, PWM2, PWM3.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CH31TOFF0 : Setting this bit will Force PWM3 to output low lasting for at most one period cycle as long as ACMP0 trigger it this feature is usually in step motor application.
Note: Only for PWM0, PWM1, PWM2, PWM3.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CMP0SEL : CMP0SEL\nSelect the positive input source of ACMP0.
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 0
Select P1.5 as the input of ACMP0
#01 : 1
Select P1.0 as the input of ACMP0
#10 : 2
Select P1.2 as the input of ACMP0
#11 : 3
Select P1.3 as the input of ACMP0
End of enumeration elements list.
T0 : Timer0 trigger PWM function Enable Control\nWhen this bit is set, timer0 time-out event will update PHCHG with PHCHG_NXT register.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CE0 : ACMP0 Trigger Function Enable Control\nNote: This bit will be auto cleared when ACMP0 trigger PWM if ACCNT0 is set.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
Next Phase Change Register
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0 : D0: when PWM0 is zero, channel 0's output waveform is D0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output low
#1 : 1
Output high
End of enumeration elements list.
D1 : D1: when PWM1 is zero, channel 1's output waveform is D1.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output low
#1 : 1
Output high
End of enumeration elements list.
D2 : D2: when PWM2 is zero, channel 2's output waveform is D2.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output low
#1 : 1
Output high
End of enumeration elements list.
D3 : D3: when PWM3 is zero, channel 3's output waveform is D3.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output low
#1 : 1
Output high
End of enumeration elements list.
D4 : D4: when PWM4 is zero, channel 4's output waveform is D4.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output low
#1 : 1
Output high
End of enumeration elements list.
D5 : D5: when PWM5 is zero, channel 5's output waveform is D5.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output low
#1 : 1
Output high
End of enumeration elements list.
D6 : D6: when MASK6 is 1, channel 6's output waveform is D6.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output low
#1 : 1
Output high
End of enumeration elements list.
D7 : D7: when MASK1 is 1, channel 7's output waveform is D7.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output low
#1 : 1
Output high
End of enumeration elements list.
PWM0 : PWM Channel 0 Output Enable Control
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output the original channel 0 waveform
#1 : 1
Output D0 specified in bit 0 of PHCHG register
End of enumeration elements list.
PWM1 : PWM Channel 1 Output Enable Control
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output the original channel 1 waveform
#1 : 1
Output D1 specified in bit 1 of PHCHG register
End of enumeration elements list.
PWM2 : PWM Channel 2 Output Enable Control
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output the original channel 2 waveform
#1 : 1
Output D2 specified in bit 2 of PHCHG register
End of enumeration elements list.
PWM3 : PWM Channel 3 Output Enable Control
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output the original channel 3 waveform
#1 : 1
Output D3 specified in bit 3 of PHCHG register
End of enumeration elements list.
PWM4 : PWM Channel 4 Output Enable Control
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output the original channel 4 waveform
#1 : 1
Output D4 specified in bit 4 of PHCHG register
End of enumeration elements list.
PWM5 : PWM Channel 5 Output Enable Control
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output the original channel 5 waveform
#1 : 1
Output D5 specified in bit 5 of PHCHG register
End of enumeration elements list.
ACCNT0 : Hardware auto clear CE0 when ACMP0 trigger it.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enabled
#1 : 1
Disabled
End of enumeration elements list.
ACCNT1 : Hardware auto clear CE1 when ACMP1 trigger it.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enabled
#1 : 1
Disabled
End of enumeration elements list.
CH01TOFF1 : Setting this bit will force PWM0 to output low lasting for at most one period cycle as long as ACMP1 trigger it this feature is usually in step motor application.
Note: only for PWM0,PWM1,PWM2,PWM3.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CH11TOFF1 : Setting this bit will force PWM1 to output low lasting for at most one period cycle as long as ACMP1 trigger it this feature is usually in step motor application.
Note: Only for PWM0, PWM1, PWM2, PWM3.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CH21TOFF1 : Setting this bit will force PWM2 to output low lasting for at most one period cycle as long as ACMP1 trigger it this feature is usually in step motor application.
Note: Only for PWM0, PWM1, PWM2, PWM3.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CH31TOFF1 : Setting this bit will force PWM3 to output low lasting for at most one period cycle as long as ACMP1 trigger it this feature is usually in step motor application.
Note: Only for PWM0, PWM1, PWM2, PWM3.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CMP1SEL : CMP1SEL\nSelect the positive input source of ACMP1.
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 0
Select P3.1 as the input of ACMP1
#01 : 1
Select P3.2 as the input of ACMP1
#10 : 2
Select P3.3 as the input of ACMP1
#11 : 3
Select P3.4 as the input of ACMP1
End of enumeration elements list.
T1 : Timer1 Trigger PWM Function Enable Control\nWhen this bit is set, timer1 time-out event will update PHCHG with PHCHG_NXT register.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CE1 : ACMP1 Trigger Function Enable Control\nNote: This bit will be auto cleared when ACMP1 trigger PWM if ACCNT1 is set.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CH01TOFF0 : Setting this bit will force PWM0 to output low lasting for at most one period cycle as long as ACMP0 trigger it this feature is usually in step motor application.
Note: Only for PWM0, PWM1, PWM2, PWM3.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CH11TOFF0 : Setting this bit will force PWM1 to output low lasting for at most one period cycle as long as ACMP0 trigger it this feature is usually in step motor application.
Note: Only for PWM0, PWM1, PWM2, PWM3.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CH21TOFF0 : Setting this bit will force PWM2 to output low lasting for at most one period cycle as long as ACMP0 trigger it this feature is usually in step motor application
Note: Only for PWM0, PWM1, PWM2, PWM3.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CH31TOFF0 : Setting this bit will force PWM3 to output low lasting for at most one period cycle as long as ACMP0 trigger it this feature is usually in step motor application.
Note: Only for PWM0, PWM1, PWM2, PWM3.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CMP0SEL : CMP0SEL\nSelect the positive input source of ACMP0.
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 0
Select P1.5 as the input of ACMP0
#01 : 1
Select P1.0 as the input of ACMP0
#10 : 2
Select P1.2 as the input of ACMP0
#11 : 3
Select P1.3 as the input of ACMP0
End of enumeration elements list.
T0 : Timer0 trigger PWM Function Enable Control\nWhen this bit is set, timer0 time-out event will update PHCHG with PHCHG_NXT register.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CE0 : ACMP0 Trigger Function Enable Control\nNote: This bit will be auto cleared when ACMP0 trigger PWM if ACCNT0 is set.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PWM Control Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0EN : PWM-Timer 0 Enable/Disable Start Run
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding PWM-timer running Stopped
#1 : 1
Corresponding PWM-timer start run Enabled
End of enumeration elements list.
DB_MODE : PWM Debug Mode Configuration Bit (Available in DEBUG mode only)
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safe mode: The timer is frozen and PWM outputs are shut down Safe state for the inverter. The timer can still be re-started from where it stops
#1 : 1
Normal mode: The timer continues to operate normally May be dangerous in some cases since a constant duty cycle is applied to the inverter (no more interrupts serviced)
End of enumeration elements list.
CH0INV : PWM-Timer 0 Output Inverter Enable Control
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverter Disabled
#1 : 1
Inverter Enabled
End of enumeration elements list.
CH0MOD : PWM-Timer 0 Auto-reload/One-Shot Mode\nNote: If there is a rising transition at this bit, it will cause CNR0 and CMR0 cleared.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
One-shot mode
#1 : 1
Auto-reload mode
End of enumeration elements list.
CH1EN : PWM-Timer 1 Enable/Disable Start Run
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding PWM-timer running Stopped
#1 : 1
Corresponding PWM-timer start run Enabled
End of enumeration elements list.
CH1INV : PWM-Timer 1 Output Inverter ON/OFF
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverter OFF
#1 : 1
Inverter ON
End of enumeration elements list.
CH1MOD : PWM-Timer 1 Auto-reload/One-Shot Mode\nNote: If there is a rising transition at this bit, it will cause CNR1 and CMR1 cleared.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
One-shot mode
#1 : 1
Auto-reload mode
End of enumeration elements list.
CH2EN : PWM-Timer 2 Enable/Disable Start Run
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding PWM-timer running Stopped
#1 : 1
Corresponding PWM-timer start run Enabled
End of enumeration elements list.
CH2INV : PWM-Timer 2 Output Inverter Enable Control
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverter Disabled
#1 : 1
Inverter Enabled
End of enumeration elements list.
CH2MOD : PWM-Timer 2 Auto-reload/One-Shot Mode\nNote: If there is a rising transition at this bit, it will cause CNR2 and CMR2 cleared.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
One-shot mode
#1 : 1
Auto-reload mode
End of enumeration elements list.
CH3EN : PWM-Timer 3 Enable/Disable Start Run
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding PWM-timer running Stopped
#1 : 1
Corresponding PWM-timer start run Enabled
End of enumeration elements list.
CH3INV : PWM-Timer 3 Output Inverter Enable Control
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverter Disabled
#1 : 1
Inverter Enabled
End of enumeration elements list.
CH3MOD : PWM-Timer 3 Auto-reload/One-Shot Mode\nNote: If there is a rising transition at this bit, it will cause CNR3 and CMR3 cleared.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
One-shot mode
#1 : 1
Auto-reload mode
End of enumeration elements list.
CH4EN : PWM-Timer 4 Enable/Disable Start Run
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding PWM-timer running Stopped
#1 : 1
Corresponding PWM-timer start run Enabled
End of enumeration elements list.
CH4INV : PWM-Timer 4 Output Inverter Enable Control
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverter Disabled
#1 : 1
Inverter Enabled
End of enumeration elements list.
CH4MOD : PWM-Timer 4 Auto-reload/One-Shot Mode\nNote: If there is a rising transition at this bit, it will cause CNR4 and CMR4 cleared.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
One-shot mode
#1 : 1
Auto-reload mode
End of enumeration elements list.
CH5EN : PWM-Timer 5 Enable/Disable Start Run
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding PWM-timer running Stopped
#1 : 1
Corresponding PWM-timer start run Enabled
End of enumeration elements list.
CH5INV : PWM-Timer 5 Output Inverter Enable Control
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverter Disabled
#1 : 1
Inverter Enabled
End of enumeration elements list.
CH5MOD : PWM-Timer 5 Auto-reload/One-Shot Mode\nNote: If there is a rising transition at this bit, it will cause CNR5 and CMR5 cleared.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
One-shot mode
#1 : 1
Auto-reload mode
End of enumeration elements list.
DZEN01 : Dead-zone 0 Generator Enable Control (PWM0 and PWM1 pair for PWM group)\nNote: When the dead-zone generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair for PWM group.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
DZEN23 : Dead-zone 2 Generator Enable Control (PWM2 and PWM3 pair for PWM group)\nNote: When the dead-zone generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair for PWM group.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
DZEN45 : Dead-zone 4 Generator Enable Control (PWM4 and PWM5 pair for PWM group)\nNote: When the dead-zone generator is enabled, the pair of PWM4 and PWM5 becomes a complementary pair for PWM group.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CLRPWM : Clear PWM Counter Control Bit\nNote: It is automatically cleared by hardware.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not clear PWM counter
#1 : 1
All 16-bit PWM counters cleared to 0x0000
End of enumeration elements list.
PWMMOD : PWM Operating Mode Selection
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 0
Independent mode
#01 : 1
Complementary mode
#10 : 2
Synchronized mode
#11 : 3
Reserved
End of enumeration elements list.
GRP : Group Bit
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The signals timing of all PWM channels are independent
#1 : 1
Unify the signals timing of PWM0, PWM2 and PWM4 in the same phase which is controlled by PWM0 and also unify the signals timing of PWM1, PWM3 and PWM5 in the same phase which is controlled by PWM1
End of enumeration elements list.
PWMTYPE : PWM Aligned Type Selection Bit
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge-aligned type
#1 : 1
Center-aligned type
End of enumeration elements list.
Phase Change MASK Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASK6 : MASK for D6
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Original GPIO P0.1
#1 : 1
D6
End of enumeration elements list.
MASK7 : MASK for D7
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Original GPIO P0.0
#1 : 1
D7
End of enumeration elements list.
CMPMASK0 : MASK for ACMP0
Note: Register CMP0CR is describe in Comparator Controller chapter
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
The input of ACMP is controlled by CMP0CR
#1 : 1
The input of ACMP is controlled by CMP0SEL of PHCHG register
End of enumeration elements list.
CMPMASK1 : MASK for ACMP1\nNote: Register CMP1CR is describe in Comparator Controller chapter
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
The input of ACMP is controlled by CMP1CR
#1 : 1
The input of ACMP is controlled by CMP1SEL of PHCHG register
End of enumeration elements list.
Period Interrupt Accumulation Control Register
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTACCUEN0 : Interrupt Accumulation Function Enable Control
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PERIODCNT : Interrupt Accumulation Bits\nWhen INTACCUEN0 is set, PERIODCNT will decrease when every PWMPIF0 flag is set and when PERIODCNT reach to zero, the PWM0 interrupt will occurred and PERIODCNT will reload itself.
bits : 4 - 7 (4 bit)
access : read-write
PWM Counter Register 0
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNRn : PWM Counter/Timer Loaded Value\nNote: Any write to CNRn will take effect in next PWM cycle.
bits : 0 - 15 (16 bit)
access : read-write
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