\n
address_offset : 0x0 Bytes (0x0)
size : 0x8C byte (0x0)
mem_usage : registers
protection : not protected
IRQ0 (BOD) Interrupt Source Identity
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source\nDefine the interrupt sources for interrupt event.
bits : 0 - 3 (4 bit)
access : read-only
IRQ4 (GPA/B) Interrupt Source Identity
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ5 (GPC/E/F) Interrupt Source Identity
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ6 (PWMA) Interrupt Source Identity
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ7 (PWMB) Interrupt Source Identity
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ8 (TMR0) Interrupt Source Identity
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ9 (TMR1) Interrupt Source Identity
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ10 (TMR2) Interrupt Source Identity
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ11 (TMR3) Interrupt Source Identity
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ12 (UART0/2) Interrupt Source Identity
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ13 (UART1) Interrupt Source Identity
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ14 (SPI0) Interrupt Source Identity
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ15 (SPI1) Interrupt Source Identity
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ1 (WDT) Interrupt Source Identity
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Reserved.
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Reserved.
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ18 (I2C0) Interrupt Source Identity
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ19 (I2C1) Interrupt Source Identity
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Reserved.
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Reserved.
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Reserved.
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ23 (USBD) Interrupt Source Identity
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Reserved.
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Reserved.
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ26 (PDMA) Interrupt Source Identity
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Reserved.
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ28 (PWRWU) Interrupt Source Identity
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ29 (ADC) Interrupt Source Identity
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ30 (IRC) Interrupt Source Identity
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ31 (RTC) Interrupt Source Identity
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ2 (EINT0) Interrupt Source Identity
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NMI Source Interrupt Select Control Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NMI_SEL : NMI Interrupt Source Selection\nThe NMI interrupt to Cortex-M0 can be selected from one of the peripheral interrupt by setting NMI_SEL.
bits : 0 - 4 (5 bit)
access : read-write
NMI_EN : NMI Interrupt Enable Bit (Write Protect)\nNote: This bit is the protected bit, and programming it needs to write '59h', '16h', and '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
NMI interrupt Disabled
#1 : 1
NMI interrupt Enabled
End of enumeration elements list.
MCU Interrupt Request Source Register
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_IRQ : MCU IRQ Source Register\nThe MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0. There are two modes to generate interrupt to Cortex-M0, the normal mode and test mode.\nThe MCU_IRQ collects all interrupts from each peripheral and synchronizes them and interrupts the Cortex-M0.\nWhen the MCU_IRQ[n] is 0: Set MCU_IRQ[n] 1 will generate an interrupt to Cortex-M0 NVIC[n].\nWhen the MCU_IRQ[n] is 1 (mean an interrupt is assert), setting 1 to the MCU_IRQ[n] 1 will clear the interrupt and setting MCU_IRQ[n] 0: has no effect
bits : 0 - 31 (32 bit)
access : read-write
MCU Interrupt Request Control Register
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FAST_IRQ : Fast IRQ Latency Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
MCU IRQ latency is fixed at 13 clock cycles of HCLK, MCU will enter IRQ handler after this fixed latency when interrupt happened
#1 : 1
MCU IRQ latency will not fixed, MCU will enter IRQ handler as soon as possible when interrupt happened
End of enumeration elements list.
IRQ3 (EINT1) Interrupt Source Identity
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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