\n
address_offset : 0x0 Bytes (0x0)
size : 0x48 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x50 Bytes (0x0)
size : 0x48 byte (0x0)
mem_usage : registers
protection : not protected
PWM Prescaler Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CP01 : Clock Prescaler 0 (PWM-Timer 0 / 1 For Group A And PWM-Timer 4 / 5 For Group B)\nClock input is divided by (CP01 + 1) before it is fed to the corresponding PWM-timer
bits : 0 - 7 (8 bit)
access : read-write
CP23 : Clock Prescaler 2 (PWM-Timer2 / 3 For Group A)\nClock input is divided by (CP23 + 1) before it is fed to the corresponding PWM-timer
bits : 8 - 15 (8 bit)
access : read-write
DZI01 : Dead-Zone Interval For Pair Of Channel 0 And Channel 1 (PWM0 And PWM1 Pair For PWM Group A, PWM4 And PWM5 Pair For PWM Group B)\nThese 8-bit determine the Dead-zone length.
bits : 16 - 23 (8 bit)
access : read-write
DZI23 : Dead-Zone Interval For Pair Of Channel2 And Channel3 (PWM2 And PWM3 Pair For PWM Group A)\nThese 8-bit determine the Dead-zone length.
bits : 24 - 31 (8 bit)
access : read-write
PWM Comparator Register 0
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMRx : PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write to CNR will take effect in next PWM cycle.
bits : 0 - 15 (16 bit)
access : read-write
PWM Data Register 0
address_offset : 0x14 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PDRx : PWM Data Register\nUser can monitor PDR to know the current value in 16-bit counter.
bits : 0 - 15 (16 bit)
access : read-only
PWM Counter Register 1
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Comparator Register 1
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Data Register 1
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Counter Register 2
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Comparator Register 2
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Data Register 2
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Counter Register 3
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Comparator Register 3
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Data Register 3
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Backward Compatible Register
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BCn : PWM Backward Compatible Register\nRefer to the CCR0/CCR2 register bit 6, 7, 22, 23 description\nNote: It is recommended that this bit be set to 1 to prevent CFLRIx and CRLRIx from being cleared when writing CCR0/CCR2.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configure write 0 to clear CFLRI0~3 and CRLRI0~3
#1 : 1
Configure write 1 to clear CFLRI0~3 and CRLRI0~3
End of enumeration elements list.
PWM Clock Source Divider Select Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSR0 : PWM Timer 0 Clock Source Divider Selection (PWM Timer 0 For Group A And PWM Timer 4 For Group B)\nSelect clock source divider for PWM timer 0.\n(Table is the same as CSR3)
bits : 0 - 2 (3 bit)
access : read-write
CSR1 : PWM Timer 1 Clock Source Divider Selection (PWM Timer 1 For Group A And PWM Timer 5 For Group B)\nSelect clock source divider for PWM timer 1.\n(Table is the same as CSR3)
bits : 4 - 6 (3 bit)
access : read-write
CSR2 : PWM Timer 2 Clock Source Divider Selection (PWM Timer 2 For Group A)\nSelect clock source divider for PWM timer 2.\n(Table is the same as CSR3)
bits : 8 - 10 (3 bit)
access : read-write
CSR3 : PWM Timer 3 Clock Source Divider Selection (PWM Timer 3 For Group A)\nSelect clock source divider for PWM timer 3.
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#000 : 0
2
#001 : 1
4
#010 : 2
8
#011 : 3
16
#100 : 4
1
End of enumeration elements list.
PWM Interrupt Enable Register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWMIE0 : PWM Channel 0 Period Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PWMIE1 : PWM Channel 1 Period Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PWMIE2 : PWM Channel 2 Period Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PWMIE3 : PWM Channel 3 Period Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PWMDIE0 : PWM Channel 0 Duty Interrupt Enable Bit
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PWMDIE1 : PWM Channel 1 Duty Interrupt Enable Bit
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PWMDIE2 : PWM Channel 2 Duty Interrupt Enable Bit
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PWMDIE3 : PWM Channel 3 Duty Interrupt Enable Bit
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
INT01TYPE : PWM01 Interrupt Period Type Selection Bit (PWM0 And PWM1 Pair For PWM Group A, PWM4 And PWM5 Pair For PWM Group B)\nNote: This bit is effective when PWM in Center-aligned type only.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMIFn will be set if PWM counter underflow
#1 : 1
PWMIFn will be set if PWM counter matches CNRn register
End of enumeration elements list.
INT23TYPE : PWM23 Interrupt Period Type Selection Bit (PWM2 And PWM3 Pair For PWM Group A)\nNote: This bit is effective when PWM in Center-aligned type only.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMIFn will be set if PWM counter underflow
#1 : 1
PWMIFn will be set if PWM counter matches CNRn register
End of enumeration elements list.
PWM Interrupt Indication Register
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWMIF0 : PWM Channel 0 Period Interrupt Status\nThis bit is set by hardware when PWM0 counter reaches the requirement of interrupt (depend on INT01TYPE bit of PIER register), software can write 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write
PWMIF1 : PWM Channel 1 Period Interrupt Status\nThis bit is set by hardware when PWM1 counter reaches the requirement of interrupt (depend on INT01TYPE bit of PIER register), software can write 1 to clear this bit to 0.
bits : 1 - 1 (1 bit)
access : read-write
PWMIF2 : PWM Channel 2 Period Interrupt Status\nThis bit is set by hardware when PWM2 counter reaches the requirement of interrupt (depend on INT23TYPE bit of PIER register), software can write 1 to clear this bit to 0.
bits : 2 - 2 (1 bit)
access : read-write
PWMIF3 : PWM Channel 3 Period Interrupt Status\nThis bit is set by hardware when PWM3 counter reaches the requirement of interrupt (depend on INT23TYPE bit of PIER register), software can write 1 to clear this bit to 0.
bits : 3 - 3 (1 bit)
access : read-write
PWMDIF0 : PWM Channel 0 Duty Interrupt Flag\nFlag is set by hardware when channel 0 PWM counter down count and reaches CMR0, software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR, this flag is not working in Edge-aligned type selection
bits : 8 - 8 (1 bit)
access : read-write
PWMDIF1 : PWM Channel 1 Duty Interrupt Flag\nFlag is set by hardware when channel 1 PWM counter down count and reaches CMR1, software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR, this flag is not working in Edge-aligned type selection
bits : 9 - 9 (1 bit)
access : read-write
PWMDIF2 : PWM Channel 2 Duty Interrupt Flag\nFlag is set by hardware when channel 2 PWM counter down count and reaches CMR2, software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR, this flag is not working in Edge-aligned type selection
bits : 10 - 10 (1 bit)
access : read-write
PWMDIF3 : PWM Channel 3 Duty Interrupt Flag\nFlag is set by hardware when channel 3 PWM counter down count and reaches CMR3, software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR, this flag is not working in Edge-aligned type selection
bits : 11 - 11 (1 bit)
access : read-write
PWM Capture Control Register 0
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INV0 : Channel 0 Inverter Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverter Disabled
#1 : 1
Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer
End of enumeration elements list.
CRL_IE0 : Channel 0 Rising Latch Interrupt Enable Bit\nWhen Enabled, if Capture detects PWM group channel 0 has rising transition, Capture will issue an Interrupt.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising latch interrupt Disabled
#1 : 1
Rising latch interrupt Enabled
End of enumeration elements list.
CFL_IE0 : Channel 0 Falling Latch Interrupt Enable Bit\nWhen Enabled, if Capture detects PWM group channel 0 has falling transition, Capture will issue an Interrupt.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling latch interrupt Disabled
#1 : 1
Falling latch interrupt Enabled
End of enumeration elements list.
CAPCH0EN : Channel 0 Capture Function Enable\nWhen Enabled, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 0 Interrupt.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture function on PWM group channel 0 Disabled
#1 : 1
Capture function on PWM group channel 0 Enabled
End of enumeration elements list.
CAPIF0 : Channel 0 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write
CRLRI0 : CRLR0 Latched Indicator\nWhen PWM group input channel 0 has a rising transition, CRLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if the BCn bit is 0, and can write 1 to clear this bit to 0 if the BCn bit is 1.
bits : 6 - 6 (1 bit)
access : read-write
CFLRI0 : CFLR0 Latched Indicator\nWhen PWM group input channel 0 has a falling transition, CFLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if the BCn bit is 0, and can write 1 to clear this bit to0 if BCn bit is 1.
bits : 7 - 7 (1 bit)
access : read-write
INV1 : Channel 1 Inverter Enable Bit
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverter Disabled
#1 : 1
Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer
End of enumeration elements list.
CRL_IE1 : Channel 1 Rising Latch Interrupt Enable Bit\nWhen Enabled, if Capture detects PWM group channel 1 has rising transition, Capture will issue an Interrupt.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising latch interrupt Disabled
#1 : 1
Rising latch interrupt Enabled
End of enumeration elements list.
CFL_IE1 : Channel 1 Falling Latch Interrupt Enable Bit\nWhen Enabled, if Capture detects PWM group channel 1 has falling transition, Capture will issue an Interrupt.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling latch interrupt Disabled
#1 : 1
Falling latch interrupt Enabled
End of enumeration elements list.
CAPCH1EN : Channel 1 Capture Function Enable Bit\nWhen Enabled, Capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 1 Interrupt.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture function on PWM group channel 1 Disabled
#1 : 1
Capture function on PWM group channel 1 Enabled
End of enumeration elements list.
CAPIF1 : Channel 1 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0.
bits : 20 - 20 (1 bit)
access : read-write
CRLRI1 : CRLR1 Latched Indicator Bit\nWhen PWM group input channel 1 has a rising transition, CRLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if BCn bit is 0, and can write 1 to clear this bit to0 if BCn bit is 1.
bits : 22 - 22 (1 bit)
access : read-write
CFLRI1 : CFLR1 Latched Indicator Bit\nWhen PWM group input channel 1 has a falling transition, CFLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if BCn bit is 0, and can write 1 to clear this bit to 0 if BCn bit is 1.
bits : 23 - 23 (1 bit)
access : read-write
PWM Capture Control Register 2
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INV2 : Channel 2 Inverter Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverter Disabled
#1 : 1
Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer
End of enumeration elements list.
CRL_IE2 : Channel 2 Rising Latch Interrupt Enable Bit\nWhen Enabled, if Capture detects PWM group channel 2 has rising transition, Capture will issue an Interrupt.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising latch interrupt Disabled
#1 : 1
Rising latch interrupt Enabled
End of enumeration elements list.
CFL_IE2 : Channel 2 Falling Latch Interrupt Enable Bit\nWhen Enabled, if Capture detects PWM group channel 2 has falling transition, Capture will issue an Interrupt.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling latch interrupt Disabled
#1 : 1
Falling latch interrupt Enabled
End of enumeration elements list.
CAPCH2EN : Channel 2 Capture Function Enable Bit\nWhen Enabled, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 2 Interrupt.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture function on PWM group channel 2 Disabled
#1 : 1
Capture function on PWM group channel 2 Enabled
End of enumeration elements list.
CAPIF2 : Channel 2 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0
bits : 4 - 4 (1 bit)
access : read-write
CRLRI2 : CRLR2 Latched Indicator\nWhen PWM group input channel 2 has a rising transition, CRLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if the BCn bit is 0, and can write 1 to clear this bit to 0 if the BCn bit is 1.
bits : 6 - 6 (1 bit)
access : read-write
CFLRI2 : CFLR2 Latched Indicator\nWhen PWM group input channel 2 has a falling transition, CFLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if BCn bit is 0, and can write 1 to clear this bit to 0 if the BCn bit is 1.
bits : 7 - 7 (1 bit)
access : read-write
INV3 : Channel 3 Inverter Enable Bit
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverter Disabled
#1 : 1
Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer
End of enumeration elements list.
CRL_IE3 : Channel 3 Rising Latch Interrupt Enable Bit\nWhen Enabled, if Capture detects PWM group channel 3 has rising transition, Capture will issue an Interrupt.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising latch interrupt Disabled
#1 : 1
Rising latch interrupt Enabled
End of enumeration elements list.
CFL_IE3 : Channel 3 Falling Latch Interrupt Enable Bit\nWhen Enabled, if Capture detects PWM group channel 3 has falling transition, Capture will issue an Interrupt.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling latch interrupt Disabled
#1 : 1
Falling latch interrupt Enabled
End of enumeration elements list.
CAPCH3EN : Channel 3 Capture Function Enable Bit\nWhen Enabled, Capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 3 Interrupt.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture function on PWM group channel 3 Disabled
#1 : 1
Capture function on PWM group channel 3 Enabled
End of enumeration elements list.
CAPIF3 : Channel 3 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0
bits : 20 - 20 (1 bit)
access : read-write
CRLRI3 : CRLR3 Latched Indicator\nWhen PWM group input channel 3 has a rising transition, CRLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if the BCn bit is 0, and can write 1 to clear this bit to 0 if the BCn bit is 1.
bits : 22 - 22 (1 bit)
access : read-write
CFLRI3 : CFLR3 Latched Indicator\nWhen PWM group input channel 3 has a falling transition, CFLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if the BCn bit is 0, and can write 1 to clear this bit to 0 if the BCn bit is 1.
bits : 23 - 23 (1 bit)
access : read-write
PWM Capture Rising Latch Register (Channel 0)
address_offset : 0x58 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CRLRx : Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition.
bits : 0 - 15 (16 bit)
access : read-only
PWM Capture Falling Latch Register (Channel 0)
address_offset : 0x5C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CFLRx : Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has Falling transition.
bits : 0 - 15 (16 bit)
access : read-only
PWM Capture Rising Latch Register (Channel 1)
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Capture Falling Latch Register (Channel 1)
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Capture Rising Latch Register (Channel 2)
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Capture Falling Latch Register (Channel 2)
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Capture Rising Latch Register (Channel 3)
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Capture Falling Latch Register (Channel 3)
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Capture Input 0~3 Enable Register
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CINEN0 : Channel 0 Capture Input Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Channel 0 capture input path Disabled. The input of PWM channel 0 capture function is always regarded as 0
#1 : 1
PWM Channel 0 capture input path Enabled. The input of PWM channel 0 capture function comes from correlative multifunction pin if GPIO multi-function is set as PWM0
End of enumeration elements list.
CINEN1 : Channel 1 Capture Input Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Channel 1 capture input path Disabled. The input of PWM channel 1 capture function is always regarded as 0
#1 : 1
PWM Channel 1 capture input path Enabled. The input of PWM channel 1 capture function comes from correlative multifunction pin if GPIO multi-function is set as PWM1
End of enumeration elements list.
CINEN2 : Channel 2 Capture Input Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Channel 2 capture input path Disabled. The input of PWM channel 2 capture function is always regarded as 0
#1 : 1
PWM Channel 2 capture input path Enabled. The input of PWM channel 2 capture function comes from correlative multifunction pin if GPIO multi-function is set as PWM2
End of enumeration elements list.
CINEN3 : Channel 3 Capture Input Enable Bit
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Channel 3 capture input path Disabled. The input of PWM channel 3 capture function is always regarded as 0
#1 : 1
PWM Channel 3 capture input path Enabled. The input of PWM channel 3 capture function comes from correlative multifunction pin if GPIO multi-function is set as PWM3
End of enumeration elements list.
PWM Output Enable for Channel 0~3
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POE0 : Channel 0 Output Enable Bit\nNote: The corresponding GPIO pin must also be switched to PWM function
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel 0 output to pin Disabled
#1 : 1
PWM channel 0 output to pin Enabled
End of enumeration elements list.
POE1 : Channel 1 Output Enable Bit\nNote: The corresponding GPIO pin must also be switched to PWM function
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel 1 output to pin Disabled
#1 : 1
PWM channel 1 output to pin Enabled
End of enumeration elements list.
POE2 : Channel 2 Output Enable Bit\nNote: The corresponding GPIO pin must also be switched to PWM function
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel 2 output to pin Disabled
#1 : 1
PWM channel 2 output to pin Enabled
End of enumeration elements list.
POE3 : Channel 3 Output Enable Bit\nNote: The corresponding GPIO pin must also be switched to PWM function
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel 3 output to pin Disabled
#1 : 1
PWM channel 3 output to pin Enabled
End of enumeration elements list.
PWM Control Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0EN : PWM-Timer 0 Enable (PWM Timer 0 For Group A And PWM Timer 4 For Group B)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding PWM-Timer stops running
#1 : 1
The corresponding PWM-Timer starts running
End of enumeration elements list.
CH0PINV : PWM-Timer 0 Output Polar Inverse Enable (PWM Timer 0 For Group A And PWM Timer 4 For Group B)
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM0 output polar inverse Disabled
#1 : 1
PWM0 output polar inverse Enabled
End of enumeration elements list.
CH0INV : PWM-Timer 0 Output Inverter Enable (PWM Timer 0 For Group A And PWM Timer 4 For Group B)
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverter Disabled
#1 : 1
Inverter Enabled
End of enumeration elements list.
CH0MOD : PWM-Timer 0 Auto-Reload/One-Shot Mode (PWM Timer 0 For Group A And PWM Timer 4 For Group B)\nNote: If there is a transition at this bit, it will cause CNR0 and CMR0 be cleared.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
One-shot mode
#1 : 1
Auto-reload mode
End of enumeration elements list.
DZEN01 : Dead-Zone 0 Generator Enable (PWM0 And PWM1 Pair For PWM Group A, PWM4 And PWM5 Pair For PWM Group B)\nNote: When Dead-zone generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair for PWM group A and the pair of PWM4 and PWM5 becomes a complementary pair for PWM group B.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
DZEN23 : Dead-Zone 2 Generator Enable (PWM2 And PWM3 Pair For PWM Group A)\nNote: When Dead-zone generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair for PWM group A.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CH1EN : PWM-Timer 1 Enable (PWM Timer 1 For Group A And PWM Timer 5 For Group B)
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding PWM-Timer Stopped
#1 : 1
Corresponding PWM-Timer Start Running
End of enumeration elements list.
CH1PINV : PWM-Timer 1 Output Polar Inverse Enable (PWM Timer 1 For Group A And PWM Timer 5 For Group B)
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM1 output polar inverse Disabled
#1 : 1
PWM1 output polar inverse Enabled
End of enumeration elements list.
CH1INV : PWM-Timer 1 Output Inverter Enable (PWM Timer 1 For Group A And PWM Timer 5 For Group B)
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverter Disable
#1 : 1
Inverter Enable
End of enumeration elements list.
CH1MOD : PWM-Timer 1 Auto-Reload/One-Shot Mode (PWM Timer 1 For Group A And PWM Timer 5 For Group B)\nNote: If there is a transition at this bit, it will cause CNR1 and CMR1 be cleared.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
One-shot mode
#1 : 1
Auto-reload mode
End of enumeration elements list.
CH2EN : PWM-Timer 2 Enable (PWM Timer 2 For Group A)
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding PWM-Timer Stopped
#1 : 1
Corresponding PWM-Timer Start Running
End of enumeration elements list.
CH2PINV : PWM-Timer 2 Output Polar Inverse Enable (PWM Timer 2 For Group A)
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM2 output polar inverse Disabled
#1 : 1
PWM2 output polar inverse Enabled
End of enumeration elements list.
CH2INV : PWM-Timer 2 Output Inverter Enable (PWM Timer 2 For Group A)
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverter Disabled
#1 : 1
Inverter Enabled
End of enumeration elements list.
CH2MOD : PWM-Timer 2 Auto-Reload/One-Shot Mode (PWM Timer 2 For Group A)\nNote: If there is a transition at this bit, it will cause CNR2 and CMR2 be cleared.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
One-shot mode
#1 : 1
Auto-reload mode
End of enumeration elements list.
CH3EN : PWM-Timer 3 Enable (PWM Timer 3 For Group A)
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding PWM-Timer Stopped
#1 : 1
Corresponding PWM-Timer Start Running
End of enumeration elements list.
CH3PINV : PWM-Timer 3 Output Polar Inverse Enable (PWM Timer 3 For Group A)
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM3 output polar inverse Disable
#1 : 1
PWM3 output polar inverse Enable
End of enumeration elements list.
CH3INV : PWM-Timer 3 Output Inverter Enable (PWM Timer 3 For Group A)
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverter Disabled
#1 : 1
Inverter Enabled
End of enumeration elements list.
CH3MOD : PWM-Timer 3 Auto-Reload/One-Shot Mode (PWM Timer 3 For Group A)\nNote: If there is a transition at this bit, it will cause CNR3 and CMR3 be cleared.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
One-shot mode
#1 : 1
Auto-reload mode
End of enumeration elements list.
PWM01TYPE : PWM01 Aligned Type Selection (PWM0 And PWM1 Pair For PWM Group A, PWM4 And PWM5 Pair For PWM Group B)
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge-aligned type
#1 : 1
Center-aligned type
End of enumeration elements list.
PWM23TYPE : PWM23 Aligned Type Selection (PWM2 And PWM3 Pair For PWM Group A)
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge-aligned type
#1 : 1
Center-aligned type
End of enumeration elements list.
PWM Trigger Control for Channel 0~3
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM0TEN : Channel 0 Center-Aligned Trigger Enable Bit\nPWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating at Center-aligned type.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel 0 trigger ADC function Disabled
#1 : 1
PWM channel 0 trigger ADC function Enabled
End of enumeration elements list.
PWM1TEN : Channel 1 Center-Aligned Trigger Enable Bit\nPWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating at Center-aligned type.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel 1 trigger ADC function Disabled
#1 : 1
PWM channel 1 trigger ADC function Enabled
End of enumeration elements list.
PWM2TEN : Channel 2 Center-Aligned Trigger Enable Bit\nPWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating at Center-aligned type.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel 2 trigger ADC function Disabled
#1 : 1
PWM channel 2 trigger ADC function Enabled
End of enumeration elements list.
PWM3TEN : Channel 3 Center-Aligned Trigger Enable Bit\nPWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating at Center-aligned type.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel 3 trigger ADC function Disabled
#1 : 1
PWM channel 3 trigger ADC function Enabled
End of enumeration elements list.
PWM Trigger Status Register
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM0TF : Channel 0 Center-Aligned Trigger Flag\nFor Center-aligned Operating mode, this bit is set to 1 by hardware when PWM counter up counts to CNR if PWM0TEN bit is set to 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nSoftware can write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write
PWM1TF : Channel 1 Center-Aligned Trigger Flag\nFor Center-aligned Operating mode, this bit is set to 1 by hardware when PWM counter up count to CNR if PWM1TEN bit is set to 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nSoftware can write 1 to clear this bit.
bits : 1 - 1 (1 bit)
access : read-write
PWM2TF : Channel 2 Center-Aligned Trigger Flag\nFor Center-aligned Operating mode, this bit is set to 1 by hardware when PWM counter up count to CNR if PWM2TEN bit is set to 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nSoftware can write 1 to clear this bit.
bits : 2 - 2 (1 bit)
access : read-write
PWM3TF : Channel 3 Center-Aligned Trigger Flag\nFor Center-aligned Operating mode, this bit is set to 1 by hardware when PWM counter up count to CNR if PWM3TEN bit is set to 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nSoftware can write 1 to clear this bit.
bits : 3 - 3 (1 bit)
access : read-write
PWM0 Synchronous Busy Status Register
address_offset : 0x88 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
S_BUSY : PWM Synchronous Busy\nWhen software writes CNR0/CMR0/PPR or switches PWM0 operation mode (PCR[3]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writing CNR0/CMR0/PPR or switching PWM0 operation mode (PCR[3]) to make sure previous setting has been updated completely.\nThis bit will be set when software writes CNR0/CMR0/PPR or switches PWM0 operation mode (PCR[3]) and will be cleared by hardware automatically when PWM update these value completely.
bits : 0 - 0 (1 bit)
access : read-only
PWM1 Synchronous Busy Status Register
address_offset : 0x8C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
S_BUSY : PWM Synchronous Busy\nWhen Software writes CNR1/CMR1/PPR or switches PWM1 operation mode (PCR[11]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writing CNR1/CMR1/PPR or switching PWM1 operation mode (PCR[11]) to make sure previous setting has been updated completely.\nThis bit will be set when software writes CNR1/CMR1/PPR or switches PWM1 operation mode (PCR[11]) and will be cleared by hardware automatically when PWM update these value completely.
bits : 0 - 0 (1 bit)
access : read-only
PWM2 Synchronous Busy Status Register
address_offset : 0x90 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
S_BUSY : PWM Synchronous Busy\nWhen Software writes CNR2/CMR2/PPR or switch PWM2 operation mode (PCR[19]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writing CNR2/CMR2/PPR or switching PWM2 operation mode (PCR[19]) to make sure previous setting has been updated completely.\nThis bit will be set when software writes CNR2/CMR2/PPR or switch PWM2 operation mode (PCR[19]) and will be cleared by hardware automatically when PWM update these value completely.
bits : 0 - 0 (1 bit)
access : read-only
PWM3 Synchronous Busy Status Register
address_offset : 0x94 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
S_BUSY : PWM Synchronous Busy\nWhen Software writes CNR3/CMR3/PPR or switch PWM3 operation mode (PCR[27]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software need to check this busy status before writing CNR3/CMR3/PPR or switching PWM3 operation mode (PCR[27]) to make sure previous setting has been updated completely.\nThis bit will be set when Software writes CNR3/CMR3/PPR or switch PWM3 operation mode (PCR[27]) and will be cleared by hardware automatically when PWM update these value completely.
bits : 0 - 0 (1 bit)
access : read-only
PWM Counter Register 0
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNRx : PWM Timer Loaded Value\nCNR determines the PWM period.\nNote: Any write to CNR will take effect in next PWM cycle.\nNote: When PWM operating at Center-aligned type, CNR value should be set between 0x0000 to 0xFFFE. If CNR equal to 0xFFFF, the PWM will work unpredictable.\nNote: When CNR value is set to 0, PWM output is always high.
bits : 0 - 15 (16 bit)
access : read-write
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