\n
address_offset : 0x0 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x40 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x50 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
ADC Data Register 0
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RSLT : A/D Conversion Result\nThis field contains conversion result of ADC.
bits : 0 - 15 (16 bit)
access : read-only
OVERRUN : Overrun Flag\nIf converted data in RSLT has not been read before new conversion result is loaded to this register, OVERRUN is set to 1 and previous conversion result is gone. It is cleared by hardware after ADDR register is read.\nThis is a read only bit.
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Data in RSLT (ADDRx[15:0], x=0~11) is recent conversion result
#1 : 1
Data in RSLT (ADDRx[15:0], x=0~11) is overwritten
End of enumeration elements list.
VALID : Valid Flag\nThis bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.\nThis is a read only bit
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
Data in RSLT bits (ADDRx[15:0], x=0~7) is not valid
#1 : 1
Data in RSLT bits (ADDRx[15:0], x=0~7) is valid
End of enumeration elements list.
ADC Data Register 4
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Data Register 5
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Data Register 6
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Data Register 7
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Control Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADEN : A/D Converter Enable Bit\nBefore starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit for saving power consumption.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
ADIE : A/D Interrupt Enable Bit\nA/D conversion end interrupt request is generated if ADIE bit (ADCR[1]) is set to 1.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
A/D interrupt function Disabled
#1 : 1
A/D interrupt function Enabled
End of enumeration elements list.
ADMD : A/D Converter Operation Mode\nWhen changing the operation mode, software should disable ADST bit (ADCR[11]) firstly.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Single conversion
#01 : 1
Reserved.
#10 : 2
Single-cycle scan
#11 : 3
Continuous scan
End of enumeration elements list.
TRGS : Hardware Trigger Source\nSoftware should disable TRGEN (ADCR[8]) and ADST (ADCR[11]) before change TRGS.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
A/D conversion is started by external STADC pin
#11 : 3
A/D conversion is started by PWM Center-aligned trigger
End of enumeration elements list.
TRGCOND : External Trigger Condition\nThese two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state for edge trigger.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Low level
#01 : 1
High level
#10 : 2
Falling edge
#11 : 3
Rising edge
End of enumeration elements list.
TRGEN : Hardware Trigger Enable Bit\nEnable or disable triggering of A/D conversion by hardware (external STADC pin or PWM Center-aligned trigger).\nADC hardware trigger function is only supported in single-cycle scan mode.\nIf hardware trigger mode, the ADST bit (ADCR[11]) can be set to 1 by the selected hardware trigger source.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PTEN : PDMA Transfer Enable Bit
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA data transfer Disabled
#1 : 1
PDMA data transfer in ADDR 0~11 Enabled
End of enumeration elements list.
DIFFEN : Differential Input Mode Control
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Single-end analog input mode
#1 : 1
Differential analog input mode
End of enumeration elements list.
ADST : A/D Conversion Start\nADST bit can be set to 1 from three sources: software, PWM Center-aligned trigger and external pin STADC. ADST will be cleared to 0 by hardware automatically at the ends of single mode and single-cycle scan mode. In continuous scan mode, A/D conversion is continuously performed until software writes 0 to this bit or chip reset.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Conversion stops and A/D converter enter idle state
#1 : 1
Conversion starts
End of enumeration elements list.
DMOF : A/D Differential Input Mode Output Format
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
A/D Conversion result will be filled in RSLT at ADDRx registers with unsigned format
#1 : 1
A/D Conversion result will be filled in RSLT at ADDRx registers with 2'complement format
End of enumeration elements list.
ADC Channel Enable Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN : Analog Input Channel Enable Bit\nSet CHEN[7:0] to enable the corresponding analog input channel 7 ~ 0. If DIFFEN bit (ADCR[10]) is set to 1, only the even number channels need to be enabled.
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0 : 0
ADC input channel Disabled
1 : 1
ADC input channel Enabled
End of enumeration elements list.
PRESEL : Analog Input Channel 7 Selection
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
External analog input
#01 : 1
Internal band-gap voltage
#10 : 2
Internal temperature sensor
#11 : 3
Reserved.
End of enumeration elements list.
CHEN1 : Analog Input Channel Enable Bit 1\nSet CHEN[14:10] to enable the corresponding analog input channel 11 ~ 8. If DIFFEN bit (ADCR[10]) is set to 1, only the even number channels need to be enabled.
bits : 10 - 13 (4 bit)
access : read-write
Enumeration:
0 : 0
ADC input channel Disabled
1 : 1
ADC input channel Enabled
End of enumeration elements list.
ADC Compare Register 0
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPEN : Compare Enable Bit\nSet this bit to 1 to enable ADC controller to compare CMPD (ADCMPR0/1[27:16]) with specified channel conversion result when converted data is loaded into ADDR register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare function Disabled
#1 : 1
Compare function Enabled
End of enumeration elements list.
CMPIE : Compare Interrupt Enable Bit\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND (ADCMPR0/1[2]) and CMPMATCNT (ADCMPR0/1[11:8]), CMPF0/1 bit (ADSR[1]/[2]) will be asserted, in the meanwhile, if CMPIE (ADCMPR0/1[1]) is set to 1, a compare interrupt request is generated.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare function interrupt Disabled
#1 : 1
Compare function interrupt Enabled
End of enumeration elements list.
CMPCOND : Compare Condition\nNote: When the internal counter reaches the value to (CMPMATCNT (ADCMPR0/1[11:8])+1), the CMPF0/1 bit (ADSR[1]/[2]) will be set.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPD (ADCMPR0/1[27:16]), the internal match counter will increase one
#1 : 1
Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPD (ADCMPR0/1[27:16]), the internal match counter will increase one
End of enumeration elements list.
CMPCH : Compare Channel Selection
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
#0000 : 0
Channel 0 conversion result is selected to be compared
#0001 : 1
Channel 1 conversion result is selected to be compared
#0010 : 2
Channel 2 conversion result is selected to be compared
#0011 : 3
Channel 3 conversion result is selected to be compared
#0100 : 4
Channel 4 conversion result is selected to be compared
#0101 : 5
Channel 5 conversion result is selected to be compared
#0110 : 6
Channel 6 conversion result is selected to be compared
#0111 : 7
Channel 7 conversion result is selected to be compared
#1000 : 8
Channel 8 conversion result is selected to be compared
#1001 : 9
Channel 9 conversion result is selected to be compared
#1010 : 10
Channel 10 conversion result is selected to be compared
#1011 : 11
Channel 11 conversion result is selected to be compared
End of enumeration elements list.
CMPMATCNT : Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND (ADCMPR0/1[2]), the internal match counter will increase 1, The comparing data must successively matched with the compare condition. Once any comparing data does not match during the comparing, the internal counter will clear to 0. When the internal counter reaches the value to (CMPMATCNT (ADCMPR0/1[11:8]) +1), the CMPF0/1 bit (ADSR[1]/[2]) will be set.
bits : 8 - 11 (4 bit)
access : read-write
CMPD : Comparison Data\nThe 12-bit data is used to compare with conversion result of specified channel.\nWhen DMOF bit (ADCR[31]) is set to 0, ADC comparator compares CMPD with conversion result with unsigned format. CMPD should be filled in unsigned format.\nWhen DMOF bit (ADCR[31]) is set to 1, ADC comparator compares CMPD with conversion result with 2'complement format. CMPD should be filled in 2'complement format.
bits : 16 - 27 (12 bit)
access : read-write
ADC Compare Register 1
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Status Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADF : A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion.\nADF is set to 1 at these two conditions:\n1. When A/D conversion ends in Single mode.\n2. When A/D conversion ends on all specified channels in Scan mode.\nThis flag can be cleared by writing 1 to itself.
bits : 0 - 0 (1 bit)
access : read-write
CMPF0 : Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR0 then this bit is set to 1. And it is cleared by writing 1 to self.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Conversion result in ADDR does not meet ADCMPR0 setting
#1 : 1
Conversion result in ADDR meets ADCMPR0 setting
End of enumeration elements list.
CMPF1 : Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR1 then this bit is set to 1. And it is cleared by writing 1 to self.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Conversion result in ADDR does not meet ADCMPR1 setting
#1 : 1
Conversion result in ADDR meets ADCMPR1 setting
End of enumeration elements list.
BUSY : BUSY/IDLE\nThis bit is mirror of as ADST bit (ADCR[11]).\nIt is read only.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
A/D converter is in idle state
#1 : 1
A/D converter is busy at conversion
End of enumeration elements list.
CHANNEL : Current Conversion Channel\nIt is read only.
bits : 4 - 7 (4 bit)
access : read-write
VALID0 : Data Valid Flag\nIt is a mirror of VALID bit (ADDR0~7[17]).\nIt is read only.
bits : 8 - 15 (8 bit)
access : read-write
OVERRUN0 : Overrun Flag\nIt is a mirror to OVERRUN bit (ADDR0~7[16]).\nIt is read only.
bits : 16 - 23 (8 bit)
access : read-write
VALID1 : Data Valid Flag\nIt is a mirror of VALID bit (ADDR8~11[17]).\nIt is read only.
bits : 24 - 27 (4 bit)
access : read-write
OVERRUN1 : Overrun Flag\nIt is a mirror to OVERRUN bit (ADDR8~11[16]).\nIt is read only.
bits : 28 - 31 (4 bit)
access : read-write
ADC Data Register 1
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC PDMA Current Transfer Data Register
address_offset : 0x40 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AD_PDMA : ADC PDMA Current Transfer Data Register\nWhen PDMA transferring, read this register can monitor current PDMA transfer data.\nCurrent PDMA transfer data is the content of ADDR0 ~ ADDR11.\nThis is a read only register.
bits : 0 - 17 (18 bit)
access : read-only
ADC Data Register 8
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Data Register 9
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Data Register 10
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Data Register 11
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Data Register 2
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Data Register 3
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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