\n
address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
Dividend Source Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVIDEND : Dividend Source\nThis register is given the dividend of divider before calculation starting.
bits : 0 - 31 (32 bit)
access : read-write
Divider Status Register
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FINISH : Division Finish Flag\nThe flag will become low when the divider is in calculation. The flag will go back to high once the calculation finished.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Under Calculation
#1 : 1
Calculation finished
End of enumeration elements list.
DIV0 : Divisor Zero Warning\nNote: The DIV0 flag is used to indicate divide-by-zero situation and updated whenever DIVISOR is written. This register is read only.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
The divisor is not 0
#1 : 1
The divisor is 0
End of enumeration elements list.
Divisor Source Resister
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVISOR : Divisor Source\nThis register is given the divisor of divider before calculation starts.\nNote: When this register is written, hardware divider will start calculate.
bits : 0 - 15 (16 bit)
access : read-write
Quotient Result Resister
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QUOTIENT : Quotient Result\nThis register holds the quotient result of divider after calculation complete.
bits : 0 - 31 (32 bit)
access : read-write
Remainder Result Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REMAINDER : Remainder Result\nThe remainder of hardware divider is 16-bit sign integer (REMAINDER[15:0]), which holds the remainder result of divider after calculation complete. The remainder of hardware divider with sign extension (REMAINDER[31:16]) to 32-bit integer.\nThis register holds the remainder result of divider after calculation complete.
bits : 0 - 31 (32 bit)
access : read-write
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