\n
address_offset : 0x0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected
I2S Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2SEN : I2S Controller Enable\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
TXEN : Transmit Enable\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data transmission Disabled
#1 : 1
Data transmission Enabled
End of enumeration elements list.
RXEN : Receive Enable\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data receiving Disabled
#1 : 1
Data receiving Enabled
End of enumeration elements list.
MUTE : Transmit Mute Enable\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit data is shifted from buffer
#1 : 1
Transmit channel zero
End of enumeration elements list.
WORDWIDTH : Word Width\n
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
data is 8-bit
#01 : 1
data is 16-bit
#10 : 2
data is 24-bit
#11 : 3
data is 32-bit
End of enumeration elements list.
MONO : Monaural Data\nNote: when chip records data, only right channel data will be saved if monaural format is select.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data is stereo format
#1 : 1
Data is monaural format
End of enumeration elements list.
FORMAT : Data Format\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2S data format
#1 : 1
MSB justified data format
End of enumeration elements list.
SLAVE : Slave Mode\nI2S can operate as master or slave. For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and send bit clock from NuMicro( NUC100 series to Audio CODEC chip. In Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from outer Audio CODEC chip.\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Master mode
#1 : 1
Slave mode
End of enumeration elements list.
TXTH : Transmit FIFO Threshold Level\nIf remain data word (32 bits) in transmit FIFO is the same or less than threshold level then TXTHF flag is set.\n
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
#000 : 0
0 word data in transmit FIFO
#001 : 1
1 word data in transmit FIFO
#010 : 2
2 words data in transmit FIFO
#011 : 3
3 words data in transmit FIFO
#100 : 4
4 words data in transmit FIFO
#101 : 5
5 words data in transmit FIFO
#110 : 6
6 words data in transmit FIFO
#111 : 7
7 words data in transmit FIFO
End of enumeration elements list.
RXTH : Receive FIFO Threshold Level\nWhen received data word(s) in buffer is equal to or higher than threshold level then RXTHF flag is set.\n
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#000 : 0
1 word data in receive FIFO
#001 : 1
2 word data in receive FIFO
#010 : 2
3 word data in receive FIFO
#011 : 3
4 word data in receive FIFO
#100 : 4
5 word data in receive FIFO
#101 : 5
6 word data in receive FIFO
#110 : 6
7 word data in receive FIFO
#111 : 7
8 word data in receive FIFO
End of enumeration elements list.
MCLKEN : Master Clock Enable\nIf the external crystal clock in NuMicro( NUC100 series is frequency 2*N*256fs, software can program MCLK_DIV[2:0] in I2SCLKDIV register to get 256fs clock to audio codec chip.\n
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Master clock Disabled
#1 : 1
Master clock Enabled
End of enumeration elements list.
RCHZCEN : Right Channel Zero-cross Detection Enable\nIf this bit is set to 1, when right channel data sign bit change or next shift data bits are all zero then RZCF flag in I2SSTATUS register is set to 1.\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Right channel zero-cross detect Disabled
#1 : 1
Right channel zero-cross detect Enabled
End of enumeration elements list.
LCHZCEN : Left channel zero-cross Detect Enable\nIf this bit is set to 1, when left channel data sign bit change or next shift data bits are all zero then LZCF flag in I2SSTATUS register is set to 1.\n
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Left channel zero-cross detect Disabled
#1 : 1
Left channel zero-cross detect Enabled
End of enumeration elements list.
CLR_TXFIFO : Clear Transmit FIFO\nWrite 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and TXFIFO_LEVEL[3:0] returns 0 and transmit FIFO becomes empty but data in transmit FIFO is not changed. \nThis bit is clear by hardware automatically, read it return zero.
bits : 18 - 18 (1 bit)
access : read-write
CLR_RXFIFO : Clear Receive FIFO\nWrite 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and RXFIFO_LEVEL[3:0] returns 0 and receive FIFO becomes empty.\nThis bit is cleared by hardware automatically, read it return zero.
bits : 19 - 19 (1 bit)
access : read-write
TXDMA : Enable Transmit DMA\nWhen TX DMA is enables, I2S request DMA to transfer data from SRAM to transmit FIFO if FIFO is not full.\n
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
TX DMA Disabled
#1 : 1
TX DMA Enabled
End of enumeration elements list.
RXDMA : Enable Receive DMA\nWhen RX DMA is enabled, I2S requests DMA to transfer data from receive FIFO to SRAM if FIFO is not empty.\n
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
RX DMA Disabled
#1 : 1
RX DMA Enabled
End of enumeration elements list.
I2S Transmit FIFO Register
address_offset : 0x10 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXFIFO : Transmit FIFO Register\nI2S contains 8 words (8x32 bit) data buffer for data transmit. Write data to this register to prepare data for transmit. The remaining word number is indicated by TX_LEVEL[3:0] in I2SSTATUS.
bits : 0 - 31 (32 bit)
access : write-only
I2S Receive FIFO Register
address_offset : 0x14 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXFIFO : Receive FIFO register\nI2S contains 8 words (8x32 bit) data buffer for data receive. Read this register to get data in FIFO. The remaining data word number is indicated by RX_LEVEL[3:0] in I2SSTATUS register.
bits : 0 - 31 (32 bit)
access : read-only
I2S Clock Divider Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCLK_DIV : Master Clock Divider\nIf chip external crystal frequency is (2xMCLK_DIV)*256fs then software can program these bits to generate 256fs clock frequency to audio codec chip. If MCLK_DIV is set to 0, MCLK is the same as external clock input.\n
bits : 0 - 2 (3 bit)
access : read-write
BCLK_DIV : Bit Clock Divider\nIf I2S operates in Master mode, bit clock is provided by the NuMicro( NUC100 series. Software can program these bits to generate sampling rate clock frequency.\n
bits : 8 - 15 (8 bit)
access : read-write
I2S Interrupt Enable Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXUDFIE : Receive FIFO Underflow Interrupt Enable\nIf software read receive FIFO when it is empty then RXUDF flag in I2SSTATUS register is set to 1.\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
RXOVFIE : Receive FIFO Overflow Interrupt Enable\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
RXTHIE : Receive FIFO Threshold Level Interrupt Enable\nWhen data word in receive FIFO is equal or higher then RXTH[2:0] and the RXTHF bit is set to 1. If RXTHIE bit is enabled, interrupt occur.\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
TXUDFIE : Transmit FIFO Underflow Interrupt Enable\nInterrupt occur if this bit is set to 1 and transmit FIFO underflow flag is set to 1.\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
TXOVFIE : Transmit FIFO Overflow Interrupt Enable\nInterrupt occurs if this bit is set to 1 and transmit FIFO overflow flag is set to 1\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
TXTHIE : Transmit FIFO Threshold Level Interrupt Enable\nInterrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH[2:0].\n
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
RZCIE : Right Channel zero-cross interrupt Enable\n
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
LZCIE : Left Channel Zero-cross interrupt Enable\nInterrupt occur if this bit is set to 1 and left channel zero-cross \n
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
I2S Status Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2SINT : I2S Interrupt Flag\nIt is wire-OR of I2STXINT and I2SRXINT bits.\nThis bit is read only.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No I2S interrupt
#1 : 1
I2S interrupt
End of enumeration elements list.
I2SRXINT : I2S Receive Interrupt\nThis bit is read only.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No receive interrupt
#1 : 1
Receive interrupt
End of enumeration elements list.
I2STXINT : I2S Transmit Interrupt\nThis bit is read only
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No transmit interrupt
#1 : 1
Transmit interrupt
End of enumeration elements list.
RIGHT : Right Channel\nThis bit indicate current transmit data is belong to right channel\nThis bit is read only
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Left channel
#1 : 1
Right channel
End of enumeration elements list.
RXUDF : Receive FIFO Underflow Flag\nRead receive FIFO when it is empty, this bit set to 1 indicate underflow occur.\nWrite 1 to clear this bit to zero
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No underflow occur
#1 : 1
Underflow occur
End of enumeration elements list.
RXOVF : Receive FIFO Overflow Flag\nWhen receive FIFO is full and receive hardware attempt write to data into receive FIFO then this bit is set to 1, data in 1st buffer is overwrote.\nWrite 1 to clear this bit to 0.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
No overflow occur
#1 : 1
Overflow occur
End of enumeration elements list.
RXTHF : Receive FIFO Threshold Flag\nWhen data word(s) in receive FIFO is equal or higher than threshold value set in RXTH[2:0] the RXTHF bit becomes to 1. It keeps at 1 till RXFIFO_LEVEL[3:0] less than RXTH[1:0] after software read RXFIFO register.\nThis bit is read only.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data word(s) in FIFO is lower than threshold level
#1 : 1
Data word(s) in FIFO is equal or higher than threshold level
End of enumeration elements list.
RXFULL : Receive FIFO Full\nThis bit reflect data words number in receive FIFO is 8\nThis bit is read only.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Not full
#1 : 1
Full
End of enumeration elements list.
RXEMPTY : Receive FIFO Empty\nThis bit reflects data words number in receive FIFO is zero\nThis bit is read only.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Not empty
#1 : 1
Empty
End of enumeration elements list.
TXUDF : Transmit FIFO Underflow Flag\nWhen transmit FIFO is empty and shift logic hardware read data from data FIFO causes this set to 1.\nWrite 1 to clear this bit to 0.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
No underflow
#1 : 1
Underflow
End of enumeration elements list.
TXOVF : Transmit FIFO Overflow Flag\nWrite data to transmit FIFO when it is full and this bit set to 1\nWrite 1 to clear this bit to 0.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
No overflow
#1 : 1
Overflow
End of enumeration elements list.
TXTHF : Transmit FIFO Threshold Flag\nWhen data word(s) in transmit FIFO is equal or lower than threshold value set in TXTH[2:0] the TXTHF bit becomes to 1. It keeps at 1 till TXFIFO_LEVEL[3:0] is higher than TXTH[1:0] after software write TXFIFO register.\nThis bit is read only
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data word(s) in FIFO is higher than threshold level
#1 : 1
Data word(s) in FIFO is equal or lower than threshold level
End of enumeration elements list.
TXFULL : Transmit FIFO Full\nThis bit reflect data word number in transmit FIFO is 8\nThis bit is read only
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Not full
#1 : 1
Full
End of enumeration elements list.
TXEMPTY : Transmit FIFO Empty\nThis bit reflect data word number in transmit FIFO is zero\nThis bit is read only.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Not empty
#1 : 1
Empty
End of enumeration elements list.
TXBUSY : Transmit Busy\nThis bit is clear to 0 when all data in transmit FIFO and shift buffer is shifted out. And set to 1 when 1st data is load to shift buffer. \nThis bit is read only.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit shift buffer is empty
#1 : 1
Transmit shift buffer is busy
End of enumeration elements list.
RZCF : Right Channel Zero-cross Flag\nIt indicates right channel next sample data sign bit is changed or all data bits are zero.\nWrite 1 to clear this bit to 0.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
No zero-cross
#1 : 1
Right channel zero-cross is detected
End of enumeration elements list.
LZCF : Left Channel Zero-cross Flag\nIt indicates left channel next sample data sign bit is changed or all data bits are zero.\nWrite 1 to clear this bit to 0.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
No zero-cross
#1 : 1
Left channel zero-cross is detected
End of enumeration elements list.
RX_LEVEL : Receive FIFO Level\nThese bits indicate word number in receive FIFO\n
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0
No data
#0001 : 1
1 word in receive FIFO
#1000 : 8
8 words in receive FIFO
End of enumeration elements list.
TX_LEVEL : Transmit FIFO Level\nThese bits indicate word number in transmit FIFO\n
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
#0000 : 0
No data
#0001 : 1
1 word in transmit FIFO
#1000 : 8
8 words in transmit FIFO
End of enumeration elements list.
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