\n
address_offset : 0x0 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x100 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x180 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x40 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x80 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC0 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x200 Bytes (0x0)
size : 0x140 byte (0x0)
mem_usage : registers
protection : not protected
GPIO Port A Pin I/O Mode Control
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PMD0 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\n
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [n] pin is in INPUT mode
#01 : 1
GPIO port [n] pin is in OUTPUT mode
#10 : 2
GPIO port [n] pin is in Open-Drain mode
#11 : 3
GPIO port [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
PMD1 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\n
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [n] pin is in INPUT mode
#01 : 1
GPIO port [n] pin is in OUTPUT mode
#10 : 2
GPIO port [n] pin is in Open-Drain mode
#11 : 3
GPIO port [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
PMD2 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\n
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [n] pin is in INPUT mode
#01 : 1
GPIO port [n] pin is in OUTPUT mode
#10 : 2
GPIO port [n] pin is in Open-Drain mode
#11 : 3
GPIO port [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
PMD3 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\n
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [n] pin is in INPUT mode
#01 : 1
GPIO port [n] pin is in OUTPUT mode
#10 : 2
GPIO port [n] pin is in Open-Drain mode
#11 : 3
GPIO port [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
PMD4 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\n
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [n] pin is in INPUT mode
#01 : 1
GPIO port [n] pin is in OUTPUT mode
#10 : 2
GPIO port [n] pin is in Open-Drain mode
#11 : 3
GPIO port [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
PMD5 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\n
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [n] pin is in INPUT mode
#01 : 1
GPIO port [n] pin is in OUTPUT mode
#10 : 2
GPIO port [n] pin is in Open-Drain mode
#11 : 3
GPIO port [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
PMD6 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\n
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [n] pin is in INPUT mode
#01 : 1
GPIO port [n] pin is in OUTPUT mode
#10 : 2
GPIO port [n] pin is in Open-Drain mode
#11 : 3
GPIO port [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
PMD7 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\n
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [n] pin is in INPUT mode
#01 : 1
GPIO port [n] pin is in OUTPUT mode
#10 : 2
GPIO port [n] pin is in Open-Drain mode
#11 : 3
GPIO port [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
PMD8 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\n
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [n] pin is in INPUT mode
#01 : 1
GPIO port [n] pin is in OUTPUT mode
#10 : 2
GPIO port [n] pin is in Open-Drain mode
#11 : 3
GPIO port [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
PMD9 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\n
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [n] pin is in INPUT mode
#01 : 1
GPIO port [n] pin is in OUTPUT mode
#10 : 2
GPIO port [n] pin is in Open-Drain mode
#11 : 3
GPIO port [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
PMD10 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\n
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [n] pin is in INPUT mode
#01 : 1
GPIO port [n] pin is in OUTPUT mode
#10 : 2
GPIO port [n] pin is in Open-Drain mode
#11 : 3
GPIO port [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
PMD11 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\n
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [n] pin is in INPUT mode
#01 : 1
GPIO port [n] pin is in OUTPUT mode
#10 : 2
GPIO port [n] pin is in Open-Drain mode
#11 : 3
GPIO port [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
PMD12 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\n
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [n] pin is in INPUT mode
#01 : 1
GPIO port [n] pin is in OUTPUT mode
#10 : 2
GPIO port [n] pin is in Open-Drain mode
#11 : 3
GPIO port [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
PMD13 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\n
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [n] pin is in INPUT mode
#01 : 1
GPIO port [n] pin is in OUTPUT mode
#10 : 2
GPIO port [n] pin is in Open-Drain mode
#11 : 3
GPIO port [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
PMD14 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\n
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [n] pin is in INPUT mode
#01 : 1
GPIO port [n] pin is in OUTPUT mode
#10 : 2
GPIO port [n] pin is in Open-Drain mode
#11 : 3
GPIO port [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
PMD15 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\n
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [n] pin is in INPUT mode
#01 : 1
GPIO port [n] pin is in OUTPUT mode
#10 : 2
GPIO port [n] pin is in Open-Drain mode
#11 : 3
GPIO port [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
GPIO Port A Pin Value
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PIN0 : Port [A/B/C/D/E] Pin Values
Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 0 - 0 (1 bit)
access : read-only
PIN1 : Port [A/B/C/D/E] Pin Values
Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 1 - 1 (1 bit)
access : read-only
PIN2 : Port [A/B/C/D/E] Pin Values
Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 2 - 2 (1 bit)
access : read-only
PIN3 : Port [A/B/C/D/E] Pin Values
Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 3 - 3 (1 bit)
access : read-only
PIN4 : Port [A/B/C/D/E] Pin Values
Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 4 - 4 (1 bit)
access : read-only
PIN5 : Port [A/B/C/D/E] Pin Values
Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 5 - 5 (1 bit)
access : read-only
PIN6 : Port [A/B/C/D/E] Pin Values
Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 6 - 6 (1 bit)
access : read-only
PIN7 : Port [A/B/C/D/E] Pin Values
Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 7 - 7 (1 bit)
access : read-only
PIN8 : Port [A/B/C/D/E] Pin Values
Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 8 - 8 (1 bit)
access : read-only
PIN9 : Port [A/B/C/D/E] Pin Values
Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 9 - 9 (1 bit)
access : read-only
PIN10 : Port [A/B/C/D/E] Pin Values
Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 10 - 10 (1 bit)
access : read-only
PIN11 : Port [A/B/C/D/E] Pin Values
Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 11 - 11 (1 bit)
access : read-only
PIN12 : Port [A/B/C/D/E] Pin Values
Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 12 - 12 (1 bit)
access : read-only
PIN13 : Port [A/B/C/D/E] Pin Values
Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 13 - 13 (1 bit)
access : read-only
PIN14 : Port [A/B/C/D/E] Pin Values
Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 14 - 14 (1 bit)
access : read-only
PIN15 : Port [A/B/C/D/E] Pin Values
Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 15 - 15 (1 bit)
access : read-only
GPIO Port E Pin I/O Mode Control
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port E Pin Digital Input Path Disable Control
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port E Data Output Value
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port E Data Output Write Mask
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port E Pin Value
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port E De-bounce Enable
address_offset : 0x114 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port E Interrupt Mode Control
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port E Interrupt Enable
address_offset : 0x11C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port E Interrupt Source Flag
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port A De-bounce Enable
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBEN0 : Port [A/B/C/D/E] Input Signal De-bounce Enable
DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: It is recommended setting this bit to '0' if GPIO is chosen as power down wakeup source. If set this bit to '1', will cause GPIO to produce interrupt twice. One is caused by wake up event, the other one is caused by delayed de-bounce result.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The bit[n] de-bounce function Disabled
#1 : 1
The bit[n] de-bounce function Enabled
End of enumeration elements list.
DBEN1 : Port [A/B/C/D/E] Input Signal De-bounce Enable
DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: It is recommended setting this bit to '0' if GPIO is chosen as power down wakeup source. If set this bit to '1', will cause GPIO to produce interrupt twice. One is caused by wake up event, the other one is caused by delayed de-bounce result.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The bit[n] de-bounce function Disabled
#1 : 1
The bit[n] de-bounce function Enabled
End of enumeration elements list.
DBEN2 : Port [A/B/C/D/E] Input Signal De-bounce Enable
DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: It is recommended setting this bit to '0' if GPIO is chosen as power down wakeup source. If set this bit to '1', will cause GPIO to produce interrupt twice. One is caused by wake up event, the other one is caused by delayed de-bounce result.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The bit[n] de-bounce function Disabled
#1 : 1
The bit[n] de-bounce function Enabled
End of enumeration elements list.
DBEN3 : Port [A/B/C/D/E] Input Signal De-bounce Enable
DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: It is recommended setting this bit to '0' if GPIO is chosen as power down wakeup source. If set this bit to '1', will cause GPIO to produce interrupt twice. One is caused by wake up event, the other one is caused by delayed de-bounce result.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The bit[n] de-bounce function Disabled
#1 : 1
The bit[n] de-bounce function Enabled
End of enumeration elements list.
DBEN4 : Port [A/B/C/D/E] Input Signal De-bounce Enable
DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: It is recommended setting this bit to '0' if GPIO is chosen as power down wakeup source. If set this bit to '1', will cause GPIO to produce interrupt twice. One is caused by wake up event, the other one is caused by delayed de-bounce result.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The bit[n] de-bounce function Disabled
#1 : 1
The bit[n] de-bounce function Enabled
End of enumeration elements list.
DBEN5 : Port [A/B/C/D/E] Input Signal De-bounce Enable
DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: It is recommended setting this bit to '0' if GPIO is chosen as power down wakeup source. If set this bit to '1', will cause GPIO to produce interrupt twice. One is caused by wake up event, the other one is caused by delayed de-bounce result.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The bit[n] de-bounce function Disabled
#1 : 1
The bit[n] de-bounce function Enabled
End of enumeration elements list.
DBEN6 : Port [A/B/C/D/E] Input Signal De-bounce Enable
DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: It is recommended setting this bit to '0' if GPIO is chosen as power down wakeup source. If set this bit to '1', will cause GPIO to produce interrupt twice. One is caused by wake up event, the other one is caused by delayed de-bounce result.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The bit[n] de-bounce function Disabled
#1 : 1
The bit[n] de-bounce function Enabled
End of enumeration elements list.
DBEN7 : Port [A/B/C/D/E] Input Signal De-bounce Enable
DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: It is recommended setting this bit to '0' if GPIO is chosen as power down wakeup source. If set this bit to '1', will cause GPIO to produce interrupt twice. One is caused by wake up event, the other one is caused by delayed de-bounce result.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The bit[n] de-bounce function Disabled
#1 : 1
The bit[n] de-bounce function Enabled
End of enumeration elements list.
DBEN8 : Port [A/B/C/D/E] Input Signal De-bounce Enable
DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: It is recommended setting this bit to '0' if GPIO is chosen as power down wakeup source. If set this bit to '1', will cause GPIO to produce interrupt twice. One is caused by wake up event, the other one is caused by delayed de-bounce result.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
The bit[n] de-bounce function Disabled
#1 : 1
The bit[n] de-bounce function Enabled
End of enumeration elements list.
DBEN9 : Port [A/B/C/D/E] Input Signal De-bounce Enable
DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: It is recommended setting this bit to '0' if GPIO is chosen as power down wakeup source. If set this bit to '1', will cause GPIO to produce interrupt twice. One is caused by wake up event, the other one is caused by delayed de-bounce result.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
The bit[n] de-bounce function Disabled
#1 : 1
The bit[n] de-bounce function Enabled
End of enumeration elements list.
DBEN10 : Port [A/B/C/D/E] Input Signal De-bounce Enable
DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: It is recommended setting this bit to '0' if GPIO is chosen as power down wakeup source. If set this bit to '1', will cause GPIO to produce interrupt twice. One is caused by wake up event, the other one is caused by delayed de-bounce result.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
The bit[n] de-bounce function Disabled
#1 : 1
The bit[n] de-bounce function Enabled
End of enumeration elements list.
DBEN11 : Port [A/B/C/D/E] Input Signal De-bounce Enable
DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: It is recommended setting this bit to '0' if GPIO is chosen as power down wakeup source. If set this bit to '1', will cause GPIO to produce interrupt twice. One is caused by wake up event, the other one is caused by delayed de-bounce result.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
The bit[n] de-bounce function Disabled
#1 : 1
The bit[n] de-bounce function Enabled
End of enumeration elements list.
DBEN12 : Port [A/B/C/D/E] Input Signal De-bounce Enable
DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: It is recommended setting this bit to '0' if GPIO is chosen as power down wakeup source. If set this bit to '1', will cause GPIO to produce interrupt twice. One is caused by wake up event, the other one is caused by delayed de-bounce result.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
The bit[n] de-bounce function Disabled
#1 : 1
The bit[n] de-bounce function Enabled
End of enumeration elements list.
DBEN13 : Port [A/B/C/D/E] Input Signal De-bounce Enable
DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: It is recommended setting this bit to '0' if GPIO is chosen as power down wakeup source. If set this bit to '1', will cause GPIO to produce interrupt twice. One is caused by wake up event, the other one is caused by delayed de-bounce result.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
The bit[n] de-bounce function Disabled
#1 : 1
The bit[n] de-bounce function Enabled
End of enumeration elements list.
DBEN14 : Port [A/B/C/D/E] Input Signal De-bounce Enable
DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: It is recommended setting this bit to '0' if GPIO is chosen as power down wakeup source. If set this bit to '1', will cause GPIO to produce interrupt twice. One is caused by wake up event, the other one is caused by delayed de-bounce result.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
The bit[n] de-bounce function Disabled
#1 : 1
The bit[n] de-bounce function Enabled
End of enumeration elements list.
DBEN15 : Port [A/B/C/D/E] Input Signal De-bounce Enable
DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: It is recommended setting this bit to '0' if GPIO is chosen as power down wakeup source. If set this bit to '1', will cause GPIO to produce interrupt twice. One is caused by wake up event, the other one is caused by delayed de-bounce result.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The bit[n] de-bounce function Disabled
#1 : 1
The bit[n] de-bounce function Enabled
End of enumeration elements list.
GPIO Port A Interrupt Mode Control
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMD0 : Port [A/B/C/D/E] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
IMD1 : Port [A/B/C/D/E] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
IMD2 : Port [A/B/C/D/E] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
IMD3 : Port [A/B/C/D/E] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
IMD4 : Port [A/B/C/D/E] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
IMD5 : Port [A/B/C/D/E] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
IMD6 : Port [A/B/C/D/E] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
IMD7 : Port [A/B/C/D/E] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
IMD8 : Port [A/B/C/D/E] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
IMD9 : Port [A/B/C/D/E] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
IMD10 : Port [A/B/C/D/E] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
IMD11 : Port [A/B/C/D/E] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
IMD12 : Port [A/B/C/D/E] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
IMD13 : Port [A/B/C/D/E] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
IMD14 : Port [A/B/C/D/E] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
IMD15 : Port [A/B/C/D/E] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
De-bounce Cycle Control
address_offset : 0x180 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBCLKSEL : De-bounce sampling cycle selection\n
bits : 0 - 3 (4 bit)
access : read-write
DBCLKSRC : De-bounce counter clock source select\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
De-bounce counter clock source is the HCLK
#1 : 1
De-bounce counter clock source is the internal 10 kHz low speed oscillator
End of enumeration elements list.
ICLK_ON : Interrupt clock On mode\nIt is recommended to turn off this bit to save system power, if on special application concern.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge detection circuit is active only if the I/O pin corresponding to GPIOx_IEN bit is set to 1
#1 : 1
All I/O pins edge detection circuit is always active after reset
End of enumeration elements list.
GPIO Port A Interrupt Enable
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IF_EN0 : Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When set the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] state low-level or high-to-low change interrupt Disabled
#1 : 1
PIN[n] state low-level or high-to-low change interrupt Enabled
End of enumeration elements list.
IF_EN1 : Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When set the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] state low-level or high-to-low change interrupt Disabled
#1 : 1
PIN[n] state low-level or high-to-low change interrupt Enabled
End of enumeration elements list.
IF_EN2 : Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When set the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] state low-level or high-to-low change interrupt Disabled
#1 : 1
PIN[n] state low-level or high-to-low change interrupt Enabled
End of enumeration elements list.
IF_EN3 : Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When set the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] state low-level or high-to-low change interrupt Disabled
#1 : 1
PIN[n] state low-level or high-to-low change interrupt Enabled
End of enumeration elements list.
IF_EN4 : Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When set the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] state low-level or high-to-low change interrupt Disabled
#1 : 1
PIN[n] state low-level or high-to-low change interrupt Enabled
End of enumeration elements list.
IF_EN5 : Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When set the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] state low-level or high-to-low change interrupt Disabled
#1 : 1
PIN[n] state low-level or high-to-low change interrupt Enabled
End of enumeration elements list.
IF_EN6 : Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When set the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] state low-level or high-to-low change interrupt Disabled
#1 : 1
PIN[n] state low-level or high-to-low change interrupt Enabled
End of enumeration elements list.
IF_EN7 : Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When set the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] state low-level or high-to-low change interrupt Disabled
#1 : 1
PIN[n] state low-level or high-to-low change interrupt Enabled
End of enumeration elements list.
IF_EN8 : Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When set the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] state low-level or high-to-low change interrupt Disabled
#1 : 1
PIN[n] state low-level or high-to-low change interrupt Enabled
End of enumeration elements list.
IF_EN9 : Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When set the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] state low-level or high-to-low change interrupt Disabled
#1 : 1
PIN[n] state low-level or high-to-low change interrupt Enabled
End of enumeration elements list.
IF_EN10 : Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When set the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] state low-level or high-to-low change interrupt Disabled
#1 : 1
PIN[n] state low-level or high-to-low change interrupt Enabled
End of enumeration elements list.
IF_EN11 : Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When set the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] state low-level or high-to-low change interrupt Disabled
#1 : 1
PIN[n] state low-level or high-to-low change interrupt Enabled
End of enumeration elements list.
IF_EN12 : Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When set the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] state low-level or high-to-low change interrupt Disabled
#1 : 1
PIN[n] state low-level or high-to-low change interrupt Enabled
End of enumeration elements list.
IF_EN13 : Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When set the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] state low-level or high-to-low change interrupt Disabled
#1 : 1
PIN[n] state low-level or high-to-low change interrupt Enabled
End of enumeration elements list.
IF_EN14 : Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When set the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] state low-level or high-to-low change interrupt Disabled
#1 : 1
PIN[n] state low-level or high-to-low change interrupt Enabled
End of enumeration elements list.
IF_EN15 : Port [A/B/C/D/E] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When set the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] state low-level or high-to-low change interrupt Disabled
#1 : 1
PIN[n] state low-level or high-to-low change interrupt Enabled
End of enumeration elements list.
IR_EN0 : Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When set the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] level-high or low-to-high interrupt Disabled
#1 : 1
PIN[n] level-high or low-to-high interrupt Enabled
End of enumeration elements list.
IR_EN1 : Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When set the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] level-high or low-to-high interrupt Disabled
#1 : 1
PIN[n] level-high or low-to-high interrupt Enabled
End of enumeration elements list.
IR_EN2 : Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When set the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] level-high or low-to-high interrupt Disabled
#1 : 1
PIN[n] level-high or low-to-high interrupt Enabled
End of enumeration elements list.
IR_EN3 : Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When set the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] level-high or low-to-high interrupt Disabled
#1 : 1
PIN[n] level-high or low-to-high interrupt Enabled
End of enumeration elements list.
IR_EN4 : Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When set the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] level-high or low-to-high interrupt Disabled
#1 : 1
PIN[n] level-high or low-to-high interrupt Enabled
End of enumeration elements list.
IR_EN5 : Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When set the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] level-high or low-to-high interrupt Disabled
#1 : 1
PIN[n] level-high or low-to-high interrupt Enabled
End of enumeration elements list.
IR_EN6 : Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When set the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] level-high or low-to-high interrupt Disabled
#1 : 1
PIN[n] level-high or low-to-high interrupt Enabled
End of enumeration elements list.
IR_EN7 : Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When set the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] level-high or low-to-high interrupt Disabled
#1 : 1
PIN[n] level-high or low-to-high interrupt Enabled
End of enumeration elements list.
IR_EN8 : Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When set the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] level-high or low-to-high interrupt Disabled
#1 : 1
PIN[n] level-high or low-to-high interrupt Enabled
End of enumeration elements list.
IR_EN9 : Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When set the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] level-high or low-to-high interrupt Disabled
#1 : 1
PIN[n] level-high or low-to-high interrupt Enabled
End of enumeration elements list.
IR_EN10 : Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When set the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] level-high or low-to-high interrupt Disabled
#1 : 1
PIN[n] level-high or low-to-high interrupt Enabled
End of enumeration elements list.
IR_EN11 : Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When set the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] level-high or low-to-high interrupt Disabled
#1 : 1
PIN[n] level-high or low-to-high interrupt Enabled
End of enumeration elements list.
IR_EN12 : Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When set the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] level-high or low-to-high interrupt Disabled
#1 : 1
PIN[n] level-high or low-to-high interrupt Enabled
End of enumeration elements list.
IR_EN13 : Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When set the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] level-high or low-to-high interrupt Disabled
#1 : 1
PIN[n] level-high or low-to-high interrupt Enabled
End of enumeration elements list.
IR_EN14 : Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When set the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] level-high or low-to-high interrupt Disabled
#1 : 1
PIN[n] level-high or low-to-high interrupt Enabled
End of enumeration elements list.
IR_EN15 : Port [A/B/C/D/E] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When set the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] level-high or low-to-high interrupt Disabled
#1 : 1
PIN[n] level-high or low-to-high interrupt Enabled
End of enumeration elements list.
GPIO Port A Interrupt Source Flag
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISRC0 : Port [A/B/C/D/E] Interrupt Source Flag\nRead :\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at GPIOx[n]\nNo action
#1 : 1
Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt
End of enumeration elements list.
ISRC1 : Port [A/B/C/D/E] Interrupt Source Flag\nRead :\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at GPIOx[n]\nNo action
#1 : 1
Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt
End of enumeration elements list.
ISRC2 : Port [A/B/C/D/E] Interrupt Source Flag\nRead :\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at GPIOx[n]\nNo action
#1 : 1
Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt
End of enumeration elements list.
ISRC3 : Port [A/B/C/D/E] Interrupt Source Flag\nRead :\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at GPIOx[n]\nNo action
#1 : 1
Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt
End of enumeration elements list.
ISRC4 : Port [A/B/C/D/E] Interrupt Source Flag\nRead :\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at GPIOx[n]\nNo action
#1 : 1
Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt
End of enumeration elements list.
ISRC5 : Port [A/B/C/D/E] Interrupt Source Flag\nRead :\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at GPIOx[n]\nNo action
#1 : 1
Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt
End of enumeration elements list.
ISRC6 : Port [A/B/C/D/E] Interrupt Source Flag\nRead :\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at GPIOx[n]\nNo action
#1 : 1
Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt
End of enumeration elements list.
ISRC7 : Port [A/B/C/D/E] Interrupt Source Flag\nRead :\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at GPIOx[n]\nNo action
#1 : 1
Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt
End of enumeration elements list.
ISRC8 : Port [A/B/C/D/E] Interrupt Source Flag\nRead :\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at GPIOx[n]\nNo action
#1 : 1
Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt
End of enumeration elements list.
ISRC9 : Port [A/B/C/D/E] Interrupt Source Flag\nRead :\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at GPIOx[n]\nNo action
#1 : 1
Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt
End of enumeration elements list.
ISRC10 : Port [A/B/C/D/E] Interrupt Source Flag\nRead :\n
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at GPIOx[n]\nNo action
#1 : 1
Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt
End of enumeration elements list.
ISRC11 : Port [A/B/C/D/E] Interrupt Source Flag\nRead :\n
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at GPIOx[n]\nNo action
#1 : 1
Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt
End of enumeration elements list.
ISRC12 : Port [A/B/C/D/E] Interrupt Source Flag\nRead :\n
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at GPIOx[n]\nNo action
#1 : 1
Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt
End of enumeration elements list.
ISRC13 : Port [A/B/C/D/E] Interrupt Source Flag\nRead :\n
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at GPIOx[n]\nNo action
#1 : 1
Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt
End of enumeration elements list.
ISRC14 : Port [A/B/C/D/E] Interrupt Source Flag\nRead :\n
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at GPIOx[n]\nNo action
#1 : 1
Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt
End of enumeration elements list.
ISRC15 : Port [A/B/C/D/E] Interrupt Source Flag\nRead :\n
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at GPIOx[n]\nNo action
#1 : 1
Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt
End of enumeration elements list.
GPIO PA.0 Pin Data I/O
address_offset : 0x200 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Pxn_PDIO : GPIO Px.n Pin Data I/O\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0], read PA0_PDIO will return the value of GPIOA_PIN[0]\nNote: The write operation will not be affected by register GPIOx_DMASK
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Set corresponding GPIO pin to low
#1 : 1
Set corresponding GPIO pin to high
End of enumeration elements list.
GPIO PA.1 Pin Data I/O
address_offset : 0x204 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.2 Pin Data I/O
address_offset : 0x208 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.3 Pin Data I/O
address_offset : 0x20C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.4 Pin Data I/O
address_offset : 0x210 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.5 Pin Data I/O
address_offset : 0x214 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.6 Pin Data I/O
address_offset : 0x218 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.7 Pin Data I/O
address_offset : 0x21C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.8 Pin Data I/O
address_offset : 0x220 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.9 Pin Data I/O
address_offset : 0x224 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.10 Pin Data I/O
address_offset : 0x228 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.11 Pin Data I/O
address_offset : 0x22C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.12 Pin Data I/O
address_offset : 0x230 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.13 Pin Data I/O
address_offset : 0x234 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.14 Pin Data I/O
address_offset : 0x238 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.15 Pin Data I/O
address_offset : 0x23C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.0 Pin Data I/O
address_offset : 0x240 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.1 Pin Data I/O
address_offset : 0x244 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.2 Pin Data I/O
address_offset : 0x248 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.3 Pin Data I/O
address_offset : 0x24C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.4 Pin Data I/O
address_offset : 0x250 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.5 Pin Data I/O
address_offset : 0x254 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.6 Pin Data I/O
address_offset : 0x258 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.7 Pin Data I/O
address_offset : 0x25C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.8 Pin Data I/O
address_offset : 0x260 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.9 Pin Data I/O
address_offset : 0x264 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.10 Pin Data I/O
address_offset : 0x268 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.11 Pin Data I/O
address_offset : 0x26C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.12 Pin Data I/O
address_offset : 0x270 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.13 Pin Data I/O
address_offset : 0x274 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.14 Pin Data I/O
address_offset : 0x278 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB.15 Pin Data I/O
address_offset : 0x27C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.0 Pin Data I/O
address_offset : 0x280 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.1 Pin Data I/O
address_offset : 0x284 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.2 Pin Data I/O
address_offset : 0x288 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.3 Pin Data I/O
address_offset : 0x28C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.4 Pin Data I/O
address_offset : 0x290 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.5 Pin Data I/O
address_offset : 0x294 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.6 Pin Data I/O
address_offset : 0x298 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.7 Pin Data I/O
address_offset : 0x29C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.8 Pin Data I/O
address_offset : 0x2A0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.9 Pin Data I/O
address_offset : 0x2A4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.10 Pin Data I/O
address_offset : 0x2A8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.11 Pin Data I/O
address_offset : 0x2AC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.12 Pin Data I/O
address_offset : 0x2B0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.13 Pin Data I/O
address_offset : 0x2B4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.14 Pin Data I/O
address_offset : 0x2B8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PC.15 Pin Data I/O
address_offset : 0x2BC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.0 Pin Data I/O
address_offset : 0x2C0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.1 Pin Data I/O
address_offset : 0x2C4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.2 Pin Data I/O
address_offset : 0x2C8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.3 Pin Data I/O
address_offset : 0x2CC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.4 Pin Data I/O
address_offset : 0x2D0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.5 Pin Data I/O
address_offset : 0x2D4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.6 Pin Data I/O
address_offset : 0x2D8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.7 Pin Data I/O
address_offset : 0x2DC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.8 Pin Data I/O
address_offset : 0x2E0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.9 Pin Data I/O
address_offset : 0x2E4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.10 Pin Data I/O
address_offset : 0x2E8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.11 Pin Data I/O
address_offset : 0x2EC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.12 Pin Data I/O
address_offset : 0x2F0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.13 Pin Data I/O
address_offset : 0x2F4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.14 Pin Data I/O
address_offset : 0x2F8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PD.15 Pin Data I/O
address_offset : 0x2FC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PE.0 Pin Data I/O
address_offset : 0x300 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PE.1 Pin Data I/O
address_offset : 0x304 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PE.2 Pin Data I/O
address_offset : 0x308 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PE.3 Pin Data I/O
address_offset : 0x30C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PE.4 Pin Data I/O
address_offset : 0x310 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PE.5 Pin Data I/O
address_offset : 0x314 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PE.6 Pin Data I/O
address_offset : 0x318 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PE.7 Pin Data I/O
address_offset : 0x31C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PE.8 Pin Data I/O
address_offset : 0x320 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PE.9 Pin Data I/O
address_offset : 0x324 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PE.10 Pin Data I/O
address_offset : 0x328 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PE.11 Pin Data I/O
address_offset : 0x32C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PE.12 Pin Data I/O
address_offset : 0x330 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PE.13 Pin Data I/O
address_offset : 0x334 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PE.14 Pin Data I/O
address_offset : 0x338 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PE.15 Pin Data I/O
address_offset : 0x33C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port A Pin Digital Input Path Disable Control
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFD : GPIOx Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal, users can disable GPIO digital input path to avoid creepage\n
bits : 16 - 31 (16 bit)
access : read-write
Enumeration:
0 : 0
I/O digital input path Enabled
1 : 1
I/O digital input path Disabled (digital input tied to low)
End of enumeration elements list.
GPIO Port B Pin I/O Mode Control
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port B Pin Digital Input Path Disable Control
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port B Data Output Value
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port B Data Output Write Mask
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port B Pin Value
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port B De-bounce Enable
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port B Interrupt Mode Control
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port B Interrupt Enable
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port B Interrupt Source Flag
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port A Data Output Value
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOUT0 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode
#1 : 1
GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode
End of enumeration elements list.
DOUT1 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode
#1 : 1
GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode
End of enumeration elements list.
DOUT2 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode
#1 : 1
GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode
End of enumeration elements list.
DOUT3 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode
#1 : 1
GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode
End of enumeration elements list.
DOUT4 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode
#1 : 1
GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode
End of enumeration elements list.
DOUT5 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode
#1 : 1
GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode
End of enumeration elements list.
DOUT6 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode
#1 : 1
GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode
End of enumeration elements list.
DOUT7 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode
#1 : 1
GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode
End of enumeration elements list.
DOUT8 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode
#1 : 1
GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode
End of enumeration elements list.
DOUT9 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode
#1 : 1
GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode
End of enumeration elements list.
DOUT10 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\n
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode
#1 : 1
GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode
End of enumeration elements list.
DOUT11 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\n
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode
#1 : 1
GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode
End of enumeration elements list.
DOUT12 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\n
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode
#1 : 1
GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode
End of enumeration elements list.
DOUT13 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\n
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode
#1 : 1
GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode
End of enumeration elements list.
DOUT14 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\n
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode
#1 : 1
GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode
End of enumeration elements list.
DOUT15 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\n
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [A/B/C/D/E] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode
#1 : 1
GPIO port [A/B/C/D/E] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode
End of enumeration elements list.
GPIO Port C Pin I/O Mode Control
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port C Pin Digital Input Path Disable Control
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port C Data Output Value
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port C Data Output Write Mask
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port C Pin Value
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port C De-bounce Enable
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port C Interrupt Mode Control
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port C Interrupt Enable
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port C Interrupt Source Flag
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port A Data Output Write Mask
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMASK0 : Port [A/B/C/D/E] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT, GPIOEx_DOUT).
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding GPIOx_DOUT[n] bit can be updated
#1 : 1
The corresponding GPIOx_DOUT[n] bit is protected
End of enumeration elements list.
DMASK1 : Port [A/B/C/D/E] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT, GPIOEx_DOUT).
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding GPIOx_DOUT[n] bit can be updated
#1 : 1
The corresponding GPIOx_DOUT[n] bit is protected
End of enumeration elements list.
DMASK2 : Port [A/B/C/D/E] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT, GPIOEx_DOUT).
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding GPIOx_DOUT[n] bit can be updated
#1 : 1
The corresponding GPIOx_DOUT[n] bit is protected
End of enumeration elements list.
DMASK3 : Port [A/B/C/D/E] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT, GPIOEx_DOUT).
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding GPIOx_DOUT[n] bit can be updated
#1 : 1
The corresponding GPIOx_DOUT[n] bit is protected
End of enumeration elements list.
DMASK4 : Port [A/B/C/D/E] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT, GPIOEx_DOUT).
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding GPIOx_DOUT[n] bit can be updated
#1 : 1
The corresponding GPIOx_DOUT[n] bit is protected
End of enumeration elements list.
DMASK5 : Port [A/B/C/D/E] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT, GPIOEx_DOUT).
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding GPIOx_DOUT[n] bit can be updated
#1 : 1
The corresponding GPIOx_DOUT[n] bit is protected
End of enumeration elements list.
DMASK6 : Port [A/B/C/D/E] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT, GPIOEx_DOUT).
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding GPIOx_DOUT[n] bit can be updated
#1 : 1
The corresponding GPIOx_DOUT[n] bit is protected
End of enumeration elements list.
DMASK7 : Port [A/B/C/D/E] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT, GPIOEx_DOUT).
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding GPIOx_DOUT[n] bit can be updated
#1 : 1
The corresponding GPIOx_DOUT[n] bit is protected
End of enumeration elements list.
DMASK8 : Port [A/B/C/D/E] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT, GPIOEx_DOUT).
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding GPIOx_DOUT[n] bit can be updated
#1 : 1
The corresponding GPIOx_DOUT[n] bit is protected
End of enumeration elements list.
DMASK9 : Port [A/B/C/D/E] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT, GPIOEx_DOUT).
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding GPIOx_DOUT[n] bit can be updated
#1 : 1
The corresponding GPIOx_DOUT[n] bit is protected
End of enumeration elements list.
DMASK10 : Port [A/B/C/D/E] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT, GPIOEx_DOUT).
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding GPIOx_DOUT[n] bit can be updated
#1 : 1
The corresponding GPIOx_DOUT[n] bit is protected
End of enumeration elements list.
DMASK11 : Port [A/B/C/D/E] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT, GPIOEx_DOUT).
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding GPIOx_DOUT[n] bit can be updated
#1 : 1
The corresponding GPIOx_DOUT[n] bit is protected
End of enumeration elements list.
DMASK12 : Port [A/B/C/D/E] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT, GPIOEx_DOUT).
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding GPIOx_DOUT[n] bit can be updated
#1 : 1
The corresponding GPIOx_DOUT[n] bit is protected
End of enumeration elements list.
DMASK13 : Port [A/B/C/D/E] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT, GPIOEx_DOUT).
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding GPIOx_DOUT[n] bit can be updated
#1 : 1
The corresponding GPIOx_DOUT[n] bit is protected
End of enumeration elements list.
DMASK14 : Port [A/B/C/D/E] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT, GPIOEx_DOUT).
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding GPIOx_DOUT[n] bit can be updated
#1 : 1
The corresponding GPIOx_DOUT[n] bit is protected
End of enumeration elements list.
DMASK15 : Port [A/B/C/D/E] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT, GPIOEx_DOUT).
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding GPIOx_DOUT[n] bit can be updated
#1 : 1
The corresponding GPIOx_DOUT[n] bit is protected
End of enumeration elements list.
GPIO Port D Pin I/O Mode Control
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port D Pin Digital Input Path Disable Control
address_offset : 0xC4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port D Data Output Value
address_offset : 0xC8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port D Data Output Write Mask
address_offset : 0xCC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port D Pin Value
address_offset : 0xD0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port D De-bounce Enable
address_offset : 0xD4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port D Interrupt Mode Control
address_offset : 0xD8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port D Interrupt Enable
address_offset : 0xDC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port D Interrupt Source Flag
address_offset : 0xE0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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