\n
address_offset : 0x0 Bytes (0x0)
size : 0x48 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x50 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection : not protected
PWM Group A/B Pre-scale Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CP01 : Clock Prescaler 0 (PWM-timer 0 / 1 for group A and PWM-timer 4 / 5 for group B)
Clock input is divided by (CP01 + 1) before it is fed to the corresponding PWM-timer
bits : 0 - 7 (8 bit)
access : read-write
CP23 : Clock Prescaler 2 (PWM-timer2 / 3 for group A and PWM-timer 6 / 7 for group B)\nClock input is divided by (CP23 + 1) before it is fed to the corresponding PWM-timer\n
bits : 8 - 15 (8 bit)
access : read-write
DZI01 : Dead Zone Interval for Pair of Channel 0 and Channel 1 (PWM0 and PWM1 pair for PWM group A, PWM4 and PWM5 pair for PWM group B)\nThese 8-bit determine dead zone length.\nThe unit time of dead zone length is received from corresponding CSR bits.
bits : 16 - 23 (8 bit)
access : read-write
DZI23 : Dead Zone Interval for Pair of Channel2 and Channel3 (PWM2 and PWM3 pair for PWM group A, PWM6 and PWM7 pair for PWM group B)\nThese 8-bit determine dead zone length.\nThe unit time of dead zone length is received from corresponding CSR bits.
bits : 24 - 31 (8 bit)
access : read-write
PWM Group A/B Comparator Register 0
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMRx : PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write to CMR will take effect in next PWM cycle.
bits : 0 - 15 (16 bit)
access : read-write
PWM Group A/B Data Register 0
address_offset : 0x14 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PDRx : PWM Data Register\nUser can monitor PDR to know the current value in 16-bit down counter.
bits : 0 - 15 (16 bit)
access : read-only
PWM Group A/B Counter Register 1
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Group A/B Comparator Register 1
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Group A/B Data Register 1
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Group A/B Counter Register 2
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Group A/B Comparator Register 2
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Group A/B Data Register 2
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Group A/B Counter Register 3
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Group A/B Comparator Register 3
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Group A/B Data Register 3
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Group A/B Backward Compatible Register
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BCn : PWM Backward Compatible Register\nPlease refer to the CCR0/CCR2 register bit 6, 7, 22, 23 description
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configure write 0 to clear CFLRI0~3 and CRLRI0~3
#1 : 1
Configure write 1 to clear CFLRI0~3 and CRLRI0~3
End of enumeration elements list.
PWM Group A/B Clock Source Divider Select Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSR0 : PWM Timer 0 Clock Source Divider Selection (PWM timer 0 for group A and PWM timer 4 for group B)\nSelect clock source divider for PWM timer 0.\n(Table is the same as CSR3)
bits : 0 - 2 (3 bit)
access : read-write
CSR1 : PWM Timer 1 Clock Source Divider Selection (PWM timer 1 for group A and PWM timer 5 for group B)\nSelect clock source divider for PWM timer 1.\n(Table is the same as CSR3)
bits : 4 - 6 (3 bit)
access : read-write
CSR2 : PWM Timer 2 Clock Source Divider Selection (PWM timer 2 for group A and PWM timer 6 for group B)\nSelect clock source divider for PWM timer 2.\n(Table is the same as CSR3)
bits : 8 - 10 (3 bit)
access : read-write
CSR3 : PWM Timer 3 Clock Source Divider Selection (PWM timer 3 for group A and PWM timer 7 for group B)\n
bits : 12 - 14 (3 bit)
access : read-write
PWM Group A/B Interrupt Enable Register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWMIE0 : PWM channel 0 Interrupt Enable\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PWMIE1 : PWM channel 1 Interrupt Enable\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PWMIE2 : PWM channel 2 Interrupt Enable\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PWMIE3 : PWM channel 3 Interrupt Enable\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PWM Group A/B Interrupt Indication Register
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWMIF0 : PWM Channel 0 Interrupt Status\nThis bit is set by hardware when PWM0 down counter reaches zero if PWM3 interrupt enable bit (PWMIE0) is 1, software can write 1 to clear this bit to 0
bits : 0 - 0 (1 bit)
access : read-write
PWMIF1 : PWM Channel 1 Interrupt Status\nThis bit is set by hardware when PWM1 down counter reaches zero if PWM3 interrupt enable bit (PWMIE1) is 1, software can write 1 to clear this bit to 0
bits : 1 - 1 (1 bit)
access : read-write
PWMIF2 : PWM Channel 2 Interrupt Status\nThis bit is set by hardware when PWM2 down counter reaches zero if PWM3 interrupt enable bit (PWMIE2) is 1, software can write 1 to clear this bit to 0
bits : 2 - 2 (1 bit)
access : read-write
PWMIF3 : PWM Channel 3 Interrupt Status\nThis bit is set by hardware when PWM3 down counter reaches zero if PWM3 interrupt enable bit (PWMIE3) is 1, software can write 1 to clear this bit to 0
bits : 3 - 3 (1 bit)
access : read-write
PWM Group A/B Capture Control Register 0
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INV0 : Channel 0 Inverter Enable\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverter Disabled
#1 : 1
Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer
End of enumeration elements list.
CRL_IE0 : Channel 0 Rising Latch Interrupt Enable\nWhen Enabled, if capture detects PWM group channel 0 has rising transition, Capture issues an Interrupt.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising latch interrupt Disabled
#1 : 1
Rising latch interrupt Enabled
End of enumeration elements list.
CFL_IE0 : Channel 0 Falling Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 0 has falling transition, Capture issues an Interrupt.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling latch interrupt Disabled
#1 : 1
Falling latch interrupt Enabled
End of enumeration elements list.
CAPCH0EN : Channel 0 Capture Function Enable\nWhen Enabled, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 0 Interrupt.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture function on PWM group channel 0 Disabled
#1 : 1
Capture function on PWM group channel 0 Enabled
End of enumeration elements list.
CAPIF0 : Channel 0 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0
bits : 4 - 4 (1 bit)
access : read-write
CRLRI0 : CRLR0 Latched Indicator Bit\nWhen PWM group input channel 0 has a rising transition, CRLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if BCn bit is 0, and can write 1 to clear this bit to 0 if BCn bit is 1.
bits : 6 - 6 (1 bit)
access : read-write
CFLRI0 : CFLR0 Latched Indicator Bit\nWhen PWM group input channel 0 has a falling transition, CFLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if BCn bit is 0, and can write 1 to clear this bit to 0 if BCn bit is 1.
bits : 7 - 7 (1 bit)
access : read-write
INV1 : Channel 1 Inverter Enable\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverter Disabled
#1 : 1
Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer
End of enumeration elements list.
CRL_IE1 : Channel 1 Rising Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 1 has rising transition, Capture issues an Interrupt.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising latch interrupt Disabled
#1 : 1
Rising latch interrupt Enabled
End of enumeration elements list.
CFL_IE1 : Channel 1 Falling Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 1 has falling transition, Capture issues an Interrupt.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling latch interrupt Disabled
#1 : 1
Falling latch interrupt Enabled
End of enumeration elements list.
CAPCH1EN : Channel 1 Capture Function Enable\nWhen Enabled, Capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 1 Interrupt.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture function on PWM group channel 1 Disabled
#1 : 1
Capture function on PWM group channel 1 Enabled
End of enumeration elements list.
CAPIF1 : Channel 1 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0
bits : 20 - 20 (1 bit)
access : read-write
CRLRI1 : CRLR1 Latched Indicator Bit\nWhen PWM group input channel 1 has a rising transition, CRLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if BCn bit is 0, and can write 1 to clear this bit to 0 if BCn bit is 1.
bits : 22 - 22 (1 bit)
access : read-write
CFLRI1 : CFLR1 Latched Indicator Bit\nWhen PWM group input channel 1 has a falling transition, CFLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if BCn bit is 0, and can write 1 to clear this bit to 0 if BCn bit is 1.
bits : 23 - 23 (1 bit)
access : read-write
PWM Group A/B Capture Control Register 2
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INV2 : Channel 2 Inverter Enable\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverter Disabled
#1 : 1
Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer
End of enumeration elements list.
CRL_IE2 : Channel 2 Rising Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 2 has rising transition, Capture issues an Interrupt.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising latch interrupt Disabled
#1 : 1
Rising latch interrupt Enabled
End of enumeration elements list.
CFL_IE2 : Channel 2 Falling Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 2 has falling transition, Capture issues an Interrupt.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling latch interrupt Disabled
#1 : 1
Falling latch interrupt Enabled
End of enumeration elements list.
CAPCH2EN : Channel 2 Capture Function Enable\nWhen Enabled, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 2 Interrupt.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture function on PWM group channel 2 Disabled
#1 : 1
Capture function on PWM group channel 2 Enabled
End of enumeration elements list.
CAPIF2 : Channel 2 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0
bits : 4 - 4 (1 bit)
access : read-write
CRLRI2 : CRLR2 Latched Indicator Bit\nWhen PWM group input channel 2 has a rising transition, CRLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if BCn bit is 0, and can write 1 to clear this bit to 0 if BCn bit is 1.
bits : 6 - 6 (1 bit)
access : read-write
CFLRI2 : CFLR2 Latched Indicator Bit\nWhen PWM group input channel 2 has a falling transition, CFLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if BCn bit is 0, and can write 1 to clear this bit to 0 if BCn bit is 1.
bits : 7 - 7 (1 bit)
access : read-write
INV3 : Channel 3 Inverter Enable\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverter Disabled
#1 : 1
Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer
End of enumeration elements list.
CRL_IE3 : Channel 3 Rising Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 3 has rising transition, Capture issues an Interrupt.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising latch interrupt Disabled
#1 : 1
Rising latch interrupt Enabled
End of enumeration elements list.
CFL_IE3 : Channel 3 Falling Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 3 has falling transition, Capture issues an Interrupt.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling latch interrupt Disabled
#1 : 1
Falling latch interrupt Enabled
End of enumeration elements list.
CAPCH3EN : Channel 3 Capture Function Enable\nWhen Enabled, capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, capture does not update CRLR and CFLR, and disable PWM group channel 3 Interrupt.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture function on PWM group channel 3 Disabled
#1 : 1
Capture function on PWM group channel 3 Enabled
End of enumeration elements list.
CAPIF3 : Channel 3 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0
bits : 20 - 20 (1 bit)
access : read-write
CRLRI3 : CRLR3 Latched Indicator Bit\nWhen PWM group input channel 3 has a rising transition, CRLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if BCn bit is 0, and can write 1 to clear this bit to 0 if BCn bit is 1.
bits : 22 - 22 (1 bit)
access : read-write
CFLRI3 : CFLR3 Latched Indicator Bit\nWhen PWM group input channel 3 has a falling transition, CFLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if BCn bit is 0, and can write 1 to clear this bit to 0 if BCn bit is 1.
bits : 23 - 23 (1 bit)
access : read-write
PWM Group A/B Capture Rising Latch Register (Channel 0)
address_offset : 0x58 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CRLRx : Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition.
bits : 0 - 15 (16 bit)
access : read-only
PWM Group A/B Capture Falling Latch Register (Channel 0)
address_offset : 0x5C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CFLRx : Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has Falling transition.
bits : 0 - 15 (16 bit)
access : read-only
PWM Group A/B Capture Rising Latch Register (Channel 1)
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Group A/B Capture Falling Latch Register (Channel 1)
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Group A/B Capture Rising Latch Register (Channel 2)
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Group A/B Capture Falling Latch Register (Channel 2)
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Group A/B Capture Rising Latch Register (Channel 3)
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Group A/B Capture Falling Latch Register (Channel 3)
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Group A/B Capture Input 0~3 Enable Register
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CINEN0 : Channel 0 Capture Input Enable\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Channel 0 capture input path Disabled. The PWM channel 0 capture function's input is always saw as 0
#1 : 1
PWM Channel 0 capture input path Enabled. The PWM channel 0 capture function input comes from correlative multifunction pin if GPIO multi-function is set as PWM0
End of enumeration elements list.
CINEN1 : Channel 1 Capture Input Enable\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Channel 1 capture input path Disabled. The PWM channel 1 capture function's input is always saw as 0
#1 : 1
PWM Channel 1 capture input path Enabled. The PWM channel 1 capture function input comes from correlative multifunction pin if GPIO multi-function is set as PWM1
End of enumeration elements list.
CINEN2 : Channel 2 Capture Input Enable\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Channel 2 capture input path Disabled. The PWM channel 2 capture function's input is always saw as 0
#1 : 1
PWM Channel 2 capture input path Enabled. The PWM channel 2 capture function input comes from correlative multifunction pin if GPIO multi-function is set as PWM2
End of enumeration elements list.
CINEN3 : Channel 3 Capture Input Enable\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Channel 3 capture input path Disabled. The PWM channel 3 capture function's input is always saw as 0
#1 : 1
PWM Channel 3 capture input path Enabled. The PWM channel 3 capture function input comes from correlative multifunction pin if GPIO multi-function is set as PWM3
End of enumeration elements list.
PWM Group A/B Output Enable Register for Channel 0~3
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POE0 : Channel 0 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel 0 output to pin Disabled
#1 : 1
PWM channel 0 output to pin Enabled
End of enumeration elements list.
POE1 : Channel 1 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel 1 output to pin Disabled
#1 : 1
PWM channel 1 output to pin Enabled
End of enumeration elements list.
POE2 : Channel 2 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel 2 output to pin Disabled
#1 : 1
PWM channel 2 output to pin Enabled
End of enumeration elements list.
POE3 : Channel 3 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel 3 output to pin Disabled
#1 : 1
PWM channel 3 output to pin Enabled
End of enumeration elements list.
PWM Group A/B Control Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0EN : PWM-Timer 0 Enable (PWM Timer 0 for Group A and PWM Timer 4 for Group B)\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding PWM-Timer running Stopped
#1 : 1
Corresponding PWM-Timer start running Enabled
End of enumeration elements list.
CH0INV : PWM-Timer 0 Output Inverter Enable (PWM Timer 0 for Group A and PWM Timer 4 for Group B)\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverter Disabled
#1 : 1
Inverter Enabled
End of enumeration elements list.
CH0MOD : PWM-Timer 0 Auto-reload/One-Shot Mode (PWM Timer 0 for Group A and PWM Timer 4 for Group B)\nNote: If there is a transition at this bit, it will cause CNR0 and CMR0 be clear.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
One-Shot Mode
#1 : 1
Auto-reload Mode
End of enumeration elements list.
DZEN01 : Dead-Zone 0 Generator Enable (PWM0 and PWM1 Pair for PWM Group A, PWM4 and PWM5 Pair for PWM Group B)\nNote: When Dead-Zone Generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair for PWM group A and the pair of PWM4 and PWM5 becomes a complementary pair for PWM group B.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
DZEN23 : Dead-Zone 2 Generator Enable (PWM2 and PWM3 Pair for PWM Group A, PWM6 and PWM7 Pair for PWM Group B)\nNote: When Dead-zone Generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair for PWM group A and the pair of PWM6 and PWM7 becomes a complementary pair for PWM group B.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CH1EN : PWM-Timer 1 Enable (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding PWM-Timer running Stopped
#1 : 1
Corresponding PWM-Timer start running Enabled
End of enumeration elements list.
CH1INV : PWM-Timer 1 Output Inverter Enable (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\n
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverter Disabled
#1 : 1
Inverter Enabled
End of enumeration elements list.
CH1MOD : PWM-Timer 1 Auto-reload/One-Shot Mode (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\nNote: If there is a transition at this bit, it will cause CNR1 and CMR1 be clear.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
One-Shot Mode
#1 : 1
Auto-load Mode
End of enumeration elements list.
CH2EN : PWM-Timer 2 Enable (PWM Timer 2 for Group A and PWM Timer 6 for Group B)\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding PWM-Timer running Stopped
#1 : 1
Corresponding PWM-Timer start running Enabled
End of enumeration elements list.
CH2INV : PWM-Timer 2 Output Inverter Enable (PWM Timer 2 for Group A and PWM Timer 6 for Group B)\n
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverter Disabled
#1 : 1
Inverter Enabled
End of enumeration elements list.
CH2MOD : PWM-Timer 2 Auto-reload/One-Shot Mode (PWM timer 2 for group A and PWM timer 6 for group B)\nNote: If there is a transition at this bit, it will cause CNR2 and CMR2 be clear.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
One-Shot Mode
#1 : 1
Auto-reload Mode
End of enumeration elements list.
CH3EN : PWM-Timer 3 Enable (PWM Timer 3 for Group A and PWM Timer 7 for Group B)
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding PWM-Timer running Stopped
#1 : 1
Corresponding PWM-Timer start running Enabled
End of enumeration elements list.
CH3INV : PWM-Timer 3 Output Inverter Enable (PWM Timer 3 for Group A and PWM Timer 7 for Group B)\n
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverter Disabled
#1 : 1
Inverter Enabled
End of enumeration elements list.
CH3MOD : PWM-Timer 3 Auto-reload/One-Shot Mode (PWM Timer 3 for Group A and PWM Timer 7 for Group B)\nNote: If there is a transition at this bit, it will cause CNR3 and CMR3 be clear.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
One-Shot Mode
#1 : 1
Auto-reload Mode
End of enumeration elements list.
PWM Group A/B Counter Register 0
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNRx : PWM Timer Loaded Value\nCNR determines the PWM period.\nNote: Any write to CNR will take effect in next PWM cycle.
bits : 0 - 15 (16 bit)
access : read-write
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