SPI_CNTRL

SPI_RX0

SPI_RX1

SPI_TX0

SPI_TX1

SPI_VARCLK

SPI_DMA

SPI_CNTRL2

SPI_DIVIDER

SPI_SSR

GO_BUSY : Go and Busy Status\nDuring the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically.\nNote: All registers should be set before writing 1 to this GO_BUSY bit.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

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RX_NEG : Receive At Negative Edge\n
bits : 1 - 1 (1 bit)
access : read-write

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TX_NEG : Transmit At Negative Edge\n
bits : 2 - 2 (1 bit)
access : read-write

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TX_BIT_LEN : Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n
bits : 3 - 7 (5 bit)
access : read-write

TX_NUM : Numbers of Transmit/Receive Word\nThis field specifies how many transmit/receive word numbers should be executed in one transfer.\nNote: in Slave mode with level-trigger configuration, if TX_NUM is set to 01, the slave select pin must be kept at active state during the successive data transfer.
bits : 8 - 9 (2 bit)
access : read-write

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LSB : LSB First\n
bits : 10 - 10 (1 bit)
access : read-write

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CLKP : Clock Polarity\n
bits : 11 - 11 (1 bit)
access : read-write

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SP_CYCLE : Suspend Interval (Master Only)\n\nIf the SPI clock rate equals system clock rate, that is to say, the DIV_ONE feature is enabled, the Burst mode suspend interval period is\n(SP_CYCLE[3:0] * 2 + 3.5) * period of system clock
bits : 12 - 15 (4 bit)
access : read-write

IF : Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
bits : 16 - 16 (1 bit)
access : read-write

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IE : Interrupt Enable\n
bits : 17 - 17 (1 bit)
access : read-write

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SLAVE : Slave Mode Enable Bit\n
bits : 18 - 18 (1 bit)
access : read-write

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REORDER : Reorder Mode Selection\nNote:\nByte reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.\nIn Slave mode with level-trigger configuration, if the byte suspend function is enabled, the slave select pin must be kept at active state during the successive four bytes transfer.
bits : 19 - 20 (2 bit)
access : read-write

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TWOB : Two Bits Transfer Mode Active\nNote1: When TWOB is enabled, the serial transmitted 2-bit data output are from SPI_TX1/0, and the received 2-bit data input are put in SPI_RX1/0.\nNote2: When TWOB is enabled, the setting of TX_NUM must be programmed as 0x00
bits : 22 - 22 (1 bit)
access : read-write

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VARCLK_EN : Variable Clock Enable (Master Only)\nNote: When this VARCLK_EN bit is enabled, the setting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode)
bits : 23 - 23 (1 bit)
access : read-write

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RX : Data Receive Register\nThe Data Receive Registers hold the value of received data of the last executed transfer. Valid bits depend on the transmit bit length field in the SPI_CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08 and TX_NUM is set to 0x0, bit RX0[7:0] holds the received data. The values of the other bits are unknown.\nNote: These bits are read only.
bits : 0 - 31 (32 bit)
access : read-only

TX : Data Transmit Register\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. Valid bits depend on the transmit bit length field in the CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08 and the TX_NUM is set to 0x0, the bit TX0[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00 and TX_NUM is set to 0x1, the SPI controller will perform two 32-bit transmit/receive successive using the same setting. The transmission sequence is TX0[31:0] first and then TX1[31:0].
bits : 0 - 31 (32 bit)
access : write-only

VARCLK : Variable Clock Pattern\nThe value in this field is the frequency patterns of the SPI clock. If the bit pattern of VARCLK is '0', the output frequency of SPICLK is according the value of DIVIDER. If the bit patterns of VARCLK are '1', the output frequency of SPICLK is according the value of DIVIDER2. Refer to register SPI_DIVIDER.\nRefer to the Variable Serial Clock Frequency paragraph for more detailed description.
bits : 0 - 31 (32 bit)
access : read-write

TX_DMA_GO : Transmit DMA Start\nSet this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically.\nIf using PDMA mode to transfer data, remember not to set GO_BUSY bit of SPI_CNTRL register. The DMA controller inside SPI controller will set it automatically whenever necessary.\nHardware will clear this bit to 0 automatically after PDMA transfer done.\nNote: In DMA mode, the Burst mode is not supported.
bits : 0 - 0 (1 bit)
access : read-write

RX_DMA_GO : Receive DMA Start\nSet this bit to 1 will start the receive PDMA process. SPI controller will issue request to PDMA controller automatically.\nHardware will clear this bit to 0 automatically after PDMA transfer done.
bits : 1 - 1 (1 bit)
access : read-write

DIV_ONE : SPI Clock Divider Control Note: 1. When this bit is set as 1, both the REORDER field and the VARCLK_EN field must be configured as 0. In other words, the byte-reorder function, byte suspend function and variable clock function must be disabled. 2. When this bit is set as 1, the TX_BIT_LEN cannot be set as 1.
bits : 0 - 0 (1 bit)
access : read-write

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NOSLVSEL : Slave 3-Wire Mode Enable Bit\nThis is used to ignore the slave select signal in Slave mode. The SPI controller can work on 3 wire interface including SPICLK, SPI_MISO, and SPI_MOSI when it is set as a slave device.\nNote: In no slave select signal mode, the SS_LTRIG, SPI_SSR[4], shall be set as 1.
bits : 8 - 8 (1 bit)
access : read-write

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SLV_ABORT : Slave 3-Wire Mode Abort Control Bit\nIn normal operation, there is interrupt event when the received data meet the required bits which define in TX_BIT_LEN and TX_NUM.\nIf the received bits are less than the requirement and there is no more serial clock input over the one transfer time in Slave mode with no slave select, the user can set this bit to force the current transfer done and then the user can get a transfer done interrupt event. \nNote: It is auto cleared to 0 by hardware when the abort event is active.
bits : 9 - 9 (1 bit)
access : read-write

SSTA_INTEN : Slave 3-Wire Mode Start Interrupt Enable\nIt is used to enable interrupt when the transfer has start in Slave mode with no slave select. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, the user can set the SLV_ABORT bit to force the transfer done.\n
bits : 10 - 10 (1 bit)
access : read-write

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SLV_START_INTSTS : Slave 3-Wire Mode Start Interrupt Status\nIt is used to dedicate that the transfer has start in Slave mode with no slave select.\n
bits : 11 - 11 (1 bit)
access : read-write

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DIVIDER : Clock Divider 1 (master only)\nThe value in this field is the frequency divider for generating the serial clock on the output SPICLK. The desired frequency is obtained according to the following equation:\n\nIn Slave mode, the period of SPI clock driven by a master shall equal or over 5 times the period of PCLK. In other words, the maximum frequency of SPI clock is the fifth of the frequency of slave's PCLK.
bits : 0 - 15 (16 bit)
access : read-write

DIVIDER2 : Clock Divider 2 (Master Only)\nThe value in this field is the 2nd frequency divider for generating the serial clock on the output SPICLK. The desired frequency is obtained according to the following equation:\n\nIf VARCLK_EN is cleared to 0, this setting is unmeaning.
bits : 16 - 31 (16 bit)
access : read-write

SSR : Slave Select Control Bits (Master Only) If AUTOSS bit is cleared, writing 1 to any bit location of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state. If AUTOSS bit is set, writing 0 to any bit location of this field will keep the corresponding SPISSx0/1 line at inactive state writing 1 to any bit location of this field will select the corresponding SPISSx0/1 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. The active state of SPISSx0/1 is specified in SS_LVL. Note: SPISSx0 is also defined as slave select input in Slave mode.
bits : 0 - 1 (2 bit)
access : read-write

SS_LVL : Slave Select Active Level\nIt defines the active status of slave select signal (SPISSx0/1).\n
bits : 2 - 2 (1 bit)
access : read-write

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AUTOSS : Automatic Slave Select Enable Bit (Master only)\n
bits : 3 - 3 (1 bit)
access : read-write

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SS_LTRIG : Slave Select Level Trigger Enable Bit (Slave Only)\n
bits : 4 - 4 (1 bit)
access : read-write

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LTRIG_FLAG : Level Trigger Accomplish Flag\nWhen the SS_LTRIG bit is set in Slave mode, this bit can be read to indicate the received bit number is met the requirement or not.\nNote: This bit is READ only
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.