\n
address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected
ISP Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPEN : ISP Enable (Write-protection Bit)\nISP function enable bit. Set this bit to enable ISP function.\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
ISP function Disabled
#1 : 1
ISP function Enabled
End of enumeration elements list.
BS : Boot Select (Write-protection Bit)\nSet/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS in Config0 after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Boot from APROM
#1 : 1
Boot from LDROM
End of enumeration elements list.
APUEN : APROM Update Enable (Write-protection Bit)\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
APROM cannot be updated when the chip runs in APROM
#1 : 1
APROM can be updated when the chip runs in APROM
End of enumeration elements list.
CFGUEN : Enable Config-bits Update by ISP (Write-protection Bit)\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled ISP to update config-bits
#1 : 1
Enabled ISP to update config-bits
End of enumeration elements list.
LDUEN : LDROM Update Enable (Write-protection Bit)\nLDROM update enable bit.\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
LDROM cannot be updated
#1 : 1
LDROM can be updated when the chip runs in APROM
End of enumeration elements list.
ISPFF : ISP Fail Flag (Write-protection Bit)
This bit is set by hardware when a triggered ISP meets any of the following conditions:
(1) APROM writes to itself if APUEN is set to 0
(2) LDROM writes to itself
(3) CONFIG is erased/programmed if CFGUEN is set to 0
(4) Destination address is illegal, such as over an available range
Write 1 to clear.
bits : 6 - 6 (1 bit)
access : read-write
ISP Trigger Control Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPGO : ISP start trigger (Write-protection Bit)
Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
This bit is the protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
ISP operation is finished
#1 : 1
ISP is on going
End of enumeration elements list.
Data Flash Start Address \n(APROM Size Is Less Than 128KB) (*1)
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DFBADR : Data Flash Base Address\nThis register indicates data flash start address. It is a read only register.\nFor 128KB flash memory device, the data flash size is defined by user configuration, register content is loaded from Config1 when chip power on but for 64/32KB device, it is fixed at 0x0001_F000.
bits : 0 - 31 (32 bit)
access : read-only
Flash Access Time Control Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPSEN : Flash Power Save Enable (Write-protection Bit)\nIf CPU clock is slower than 24 MHz, then s/w can enable flash power saving function.\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flash power saving Disabled
#1 : 1
Flash power saving Enabled
End of enumeration elements list.
FATS : Flash Access Time Window Selection (Write-protection Bits)\n
bits : 1 - 3 (3 bit)
access : read-write
LFOM : Low Frequency Optimization Mode (Write-protection Bit)\nWhen chip operation frequency is lower than 25 MHz, chip can work more efficiently by setting this bit to 1\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low Frequency Optimization mode Disabled
#1 : 1
Low Frequency Optimization mode Enabled
End of enumeration elements list.
ISP Address Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPADR : ISP Address\nThe NuMicro( NUC100 Series has a maximum 32Kx32 embedded flash, which supports word program only. ISPADR[1:0] must be kept 00b for ISP operation.
bits : 0 - 31 (32 bit)
access : read-write
ISP Data Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPDAT : ISP Data\nWrite data to this register before ISP program operation\nRead data from this register after ISP read operation
bits : 0 - 31 (32 bit)
access : read-write
ISP Command Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FCTRL : ISP Command
bits : 0 - 3 (4 bit)
access : read-write
FCEN : ISP Command
bits : 4 - 4 (1 bit)
access : read-write
FOEN : ISP Command\n
bits : 5 - 5 (1 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.