TCSR2

TCAP2

TEXCON2

TEXISR2

TCSR3

TCMPR3

TISR3

TDR3

TCAP3

TEXCON3

TEXISR3

TCMPR2

TISR2

TDR2

PRESCALE : Prescale Counter\n
bits : 0 - 7 (8 bit)
access : read-write

TDR_EN : Data Load Enable Bit\nWhen this bit is set, timer counter value (TDR) will be updated continuously to monitor internal 24-bit up counter value as the counter is counting.\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WAKE_EN : Wake-up Enable Bit\nIf this bit is set to 1, while timer interrupt flag (TISR[0] TIF) is generated to 1 and IE (TCSR[29] interrupt enable bit) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.\n
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CTB : Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. When timer is used as an event counter, this bit should be set to 1 and select HCLK as timer clock source. Please refer to 6.8.4.5 for detail description.\n
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CACT : Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\n
bits : 25 - 25 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CRST : Timer Reset Bit\nSetting this bit will reset the 24-bit up counter value (TDR) and also force CEN (TCSR[30] timer enable bit) to 0 if CACT (TCSR[25] timer active status bit) is 1.\n
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE : Timer Operating Mode\n
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IE : Interrupt Enable Bit\nIf this bit is enabled, when the timer interrupt flag (TISR[0] TIF) is set to 1, the timer interrupt signal is generated and inform to CPU.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CEN : Timer Enable Bit\n
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBGACK_TMR : ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TCAP : Timer Capture Data Register When TEXEN (TEXCON[3] timer external pin enable) bit is set, RSTCAPSEL (TEXCON[4] timer external reset counter/capture mode select) bit is 0, and a transition on TxEX pin matched the TEX_EDGE (TEXCON[2:1] timer external pin edge detect) setting, TEXIF (TEXISR[0] timer external interrupt flag) will set to 1 and the current timer counter value (TDR value) will be auto-loaded into this TCAP field.
bits : 0 - 23 (24 bit)
access : read-only

TX_PHASE : Timer External Count Phase \nThis bit indicates the detection phase of external counting pin.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TEX_EDGE : Timer External Pin Edge Detect\n
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TEXEN : Timer External Pin Enable Bit\nThis bit enables the RSTCAPSEL (TEXCON[4] timer external reset counter/capture mode select ) function on the TxEX pin. \n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTCAPSEL : Timer External Reset Counter / Capture Mode Selection\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TEXIEN : Timer External Interrupt Enable Bit\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TEXDB : Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled, the edge detection of TxEX pin is detected with de-bounce circuit.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TCDB : Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TEXIF : Timer External Interrupt Flag This bit indicates the timer external interrupt flag status. When TEXEN (TEXCON[3] timer external pin enable) bit is set, RSTCAPSEL (TEXCON[4] timer external reset counter/capture mode select) bit is 0, and a transition on TxEX pin matched the TEX_EDGE (TEXCON[2:1] timer external pin edge detect) setting, this bit will set to 1 by hardware. Note: This bit is cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write

TCMP : Timer Compared Value\nTCMP is a 24-bit compared value register. When the internal 24-bit up counter value is equal to TCMP value, the TIF (TISR[0] timet interrupt flag) will set to 1.\nNote1: Never write 0x0 or 0x1 in TCMP field, or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if software writes a new value into TCMP field. But if timer is operating at other modes, the 24-bit up counter will restart counting and using newest TCMP value to be the timer compared value if software writes a new value into TCMP field.
bits : 0 - 23 (24 bit)
access : read-write

TIF : Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer.\nAnd this bit is set by hardware when the timer counter value) matches the timer compared value (TCMP value). \nNote: This bit is cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write

TWF : Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TDR : Timer Data Register\nIf TDR_EN (TCSR[16]) is set to 1, TDR will be updated continuously to monitor 24-bit timer counter value.
bits : 0 - 23 (24 bit)
access : read-only