\n
address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected
PS/2 Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS2EN : PS/2 Device Enable Bit\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PS/2 device controller Disabled
#1 : 1
PS/2 device controller Enabled
End of enumeration elements list.
TXINTEN : Transmit Interrupt Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data transmit complete interrupt Disabled
#1 : 1
Data transmit complete interrupt Enabled
End of enumeration elements list.
RXINTEN : Receive Interrupt Enable Bit\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data receive complete interrupt Disabled
#1 : 1
Data receive complete interrupt Enabled
End of enumeration elements list.
TXFIFO_DEPTH : Transmit Data FIFO Depth\nThere are 16 bytes buffer for data transmit. Software can define the FIFO depth from 1 to 16 bytes depends on application needs.\n
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : 0
1 byte
1 : 1
2 bytes
14 : 14
15 bytes
15 : 15
16 bytes
End of enumeration elements list.
ACK : Acknowledge Enable Bit\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Always send acknowledge to host at 12th clock for host to device communication
#1 : 1
If parity bit error or stop bit is not received correctly, acknowledge bit will not be sent to host at 12th clock
End of enumeration elements list.
CLRFIFO : Clear TX FIFO\nWrite 1 to this bit to terminate device to host transmission. The TXEMPTY bit in PS2STATUS bit will be set to 1 and pointer BYTEIDEX is reset to 0 regardless there is residue data in buffer or not. The buffer content is not been cleared.\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Not active
#1 : 1
Clear FIFO
End of enumeration elements list.
OVERRIDE : Software Override PS2 CLK/DATA Pin State\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
PS2CLK and PS2DATA pins are controlled by internal state machine
#1 : 1
PS2CLK and PS2DATA pins are controlled by software
End of enumeration elements list.
FPS2CLK : Force PS2CLK Line\nIt forces PS2CLK line high or low regardless of the internal state of the device controller if OVERRIDE is set to 1.\n
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Force PS2CLK line low
#1 : 1
Force PS2CLK line high
End of enumeration elements list.
FPS2DAT : Force PS2DATA Line\nIt forces PS2DATA high or low regardless of the internal state of the device controller if OVERRIDE is set to 1.\n
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Force PS2DATA low
#1 : 1
Force PS2DATA high
End of enumeration elements list.
PS/2 Transmit Data Register 3
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS/2 Receive Data Register
address_offset : 0x14 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : Received Data\nFor host to device communication, after acknowledge bit is sent, the received data is copied from receive shift register to PS2RXDATA register. CPU must read this register before next byte reception complete, otherwise the data will be overwritten and RXOVF bit in PS2STATUS[6] will be set to 1.
bits : 0 - 7 (8 bit)
access : read-only
PS/2 Status Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS2CLK : CLK Pin State\nThis bit reflects the status of the PS2CLK line after synchronizing.
bits : 0 - 0 (1 bit)
access : read-write
PS2DATA : DATA Pin State\nThis bit reflects the status of the PS2DATA line after synchronizing and sampling.
bits : 1 - 1 (1 bit)
access : read-write
FRAMERR : Frame Error
For host to device communication, this bit sets to 1 if STOP bit (logic 1) is not received. If frame error occurs, the PS2_DATA line may keep at low state after 12th clock. At this moment, software overrides PS2CLK to send clock till PS2DATA release to high state. After that, device sends a Resend command to host.
Note: This bit can be cleared by writing '1' to it.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No frame error
#1 : 1
Frame error occur
End of enumeration elements list.
RXPARITY : Received Parity (Read Only)\nThis bit reflects the parity bit for the last received data byte (odd parity).
bits : 3 - 3 (1 bit)
access : read-only
RXBUSY : Receive Busy (Read Only)\nThis bit indicates that the PS/2 device is currently receiving data.\n
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Idle
#1 : 1
Currently receiving data
End of enumeration elements list.
TXBUSY : Transmit Busy (Read Only)\nThis bit indicates that the PS/2 device is currently sending data.\n
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
Idle
#1 : 1
Currently sending data
End of enumeration elements list.
RXOVF : RX Buffer Overwrite\nNote: This bit can be cleared by writing '1' to it.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No overwrite
#1 : 1
Data in PS2RXDATA register is overwritten by new received data
End of enumeration elements list.
TXEMPTY : TX FIFO Empty (Read Only)\nWhen software writes data to PS2TXDATA0-3, the TXEMPTY bit is cleared to 0 immediately if PS2EN is enabled. When transmitted data byte number is equal to FIFODEPTH then TXEMPTY bit is set to 1.\n
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
There is data to be transmitted
#1 : 1
FIFO is empty
End of enumeration elements list.
BYTEIDX : Byte Index (Read Only)\nIt indicates which data byte in transmit data shift register. When all data in FIFO is transmitted and it will be cleared to 0.\n
bits : 8 - 11 (4 bit)
access : read-only
Enumeration:
#0000 : 0
DATA Transmit is TXDATA0[7:0]
#0001 : 1
DATA Transmit is TXDATA0[15:8]
#0010 : 2
DATA Transmit is TXDATA0[23:16]
#0011 : 3
DATA Transmit is TXDATA0[31:24]
#0100 : 4
DATA Transmit is TXDATA1[7:0]
#0101 : 5
DATA Transmit is TXDATA1[15:8]
#0110 : 6
DATA Transmit is TXDATA1[23:16]
#0111 : 7
DATA Transmit is TXDATA1[31:24]
#1000 : 8
DATA Transmit is TXDATA2[7:0]
#1001 : 9
DATA Transmit is TXDATA2[15:8]
#1010 : 10
DATA Transmit is TXDATA2[23:16]
#1011 : 11
DATA Transmit is TXDATA2[31:24]
#1100 : 12
DATA Transmit is TXDATA3[7:0]
#1101 : 13
DATA Transmit is TXDATA3[15:8]
#1110 : 14
DATA Transmit is TXDATA3[23:16]
#1111 : 15
DATA Transmit is TXDATA3[31:24]
End of enumeration elements list.
PS/2 Interrupt Identification Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXINT : Receive Interrupt\nThis bit is set to 1 when acknowledge bit is sent for Host to device communication. Interrupt occurs if RXINTEN bit is set to 1.\nNote: This bit can be cleared by writing '1' to it.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt
#1 : 1
Receive interrupt occurs
End of enumeration elements list.
TXINT : Transmit Interrupt\nThis bit is set to 1 after STOP bit is transmitted. Interrupt occur if TXINTEN bit is set to 1.\nNote: This bit can be cleared by writing '1' to it.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt
#1 : 1
Transmit interrupt occurs
End of enumeration elements list.
PS/2 Transmit Data Register 0
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS2TXDATAx : Transmit Data\nWriting data to this register starts in device to host communication if bus is in IDLE state. Software must enable PS2EN before writing data to TX buffer.
bits : 0 - 31 (32 bit)
access : read-write
PS/2 Transmit Data Register 1
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS/2 Transmit Data Register 2
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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