\n

CLK

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x30 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x70 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CLK_PWRCTL (PWRCTL)

CLK_CLKSEL0 (CLKSEL0)

CLK_CLKSEL1 (CLKSEL1)

CLK_CLKDIV0 (CLKDIV0)

CLK_CLKSEL2 (CLKSEL2)

CLK_PLLCTL (PLLCTL)

CLK_CLKOCTL (CLKOCTL)

CLK_APBCLK1 (APBCLK1)

CLK_CLKSEL3 (CLKSEL3)

CLK_AHBCLK (AHBCLK)

CLK_CLKDCTL (CLKDCTL)

CLK_CLKDSTS (CLKDSTS)

CLK_CDUPB (CDUPB)

CLK_CDLOWB (CDLOWB)

CLK_APBCLK0 (APBCLK0)

CLK_STATUS (STATUS)


CLK_PWRCTL (PWRCTL)

System Power-down Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_PWRCTL CLK_PWRCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XTLEN HIRCEN LIRCEN PDWKDLY PDWKIEN PDWKIF PDEN HXTGAIN

XTLEN : External HXT or LXT Crystal Oscillator Enable Bit (Write Protect)\nThe default clock source is from HIRC. These two bits are default set to "00" and the PF.0 and PF.1 pins are GPIO.\nNote 1: These bits are write protected. Refer to the SYS_REGLCTL register.\nNote 2: These bits are over-written by CFOSC (CONFIG0[26]) after reset.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 0

HXT LXT Disabled (default)

#01 : 1

HXT Enabled

#10 : 2

LXT Enabled

#11 : 3

Reserved

End of enumeration elements list.

HIRCEN : HIRC Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

48 MHz internal high speed RC oscillator (HIRC) Disabled

#1 : 1

48 MHz internal high speed RC oscillator (HIRC) Enabled

End of enumeration elements list.

LIRCEN : LIRC Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

10 kHz internal low speed RC oscillator (LIRC) Disabled

#1 : 1

10 kHz internal low speed RC oscillator (LIRC) Enabled

End of enumeration elements list.

PDWKDLY : Enable the Wake-up Delay Counter (Write Protect)\nWhen the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip work at 4~24 MHz external high speed crystal oscillator (HXT), and 512 clock cycles(selected by HIRCSTBS) when chip work at 48 MHz internal high speed RC oscillator (HIRC).\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock cycles delay Disabled

#1 : 1

Clock cycles delay Enabled

End of enumeration elements list.

PDWKIEN : Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)\nNote1: The interrupt will occur when both PDWKIF and PDWKIEN are high.\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Power-down mode wake-up interrupt Disabled

#1 : 1

Power-down mode wake-up interrupt Enabled

End of enumeration elements list.

PDWKIF : Power-down Mode Wake-up Interrupt Status\nSet by "Power-down wake-up event", it indicates that resume from Power-down mode" \nThe flag is set if the EINT0~5, GPIO, USBD, UART0, WDT, BOD, TMR0~3 or I2C0~1 wake-up occurred.\nNote1: Write 1 to clear the bit to 0.\nNote2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1.
bits : 6 - 6 (1 bit)
access : read-write

PDEN : System Power-down Enable (Write Protect)\nWhen this bit is set to 1, Power-down mode is enabled and chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode.\nWhen chip wakes up from Power-down mode, this bit is auto cleared. Users need to set this bit again for next Power-down.\nIn Power-down mode, HXT and the HIRC will be disabled in this mode, but LXT and LIRC are not controlled by Power-down mode.\nIn Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Chip operating normally or chip in idle mode because of WFI command

#1 : 1

Chip enters Power-down mode instant or wait CPU sleep command WFI

End of enumeration elements list.

HXTGAIN : HXT Gain Control Bit (Write Protect)\nThis is a protected register. Please refer to open lock sequence to program it.\nGain control is used to enlarge the gain of crystal to make sure crystal work normally. If gain control is enabled, crystal will consume more power than gain control off. \nNote 1: These bits are write protected. Refer to the SYS_REGLCTL register.\nNote 2: These bits are over-written by CFGXT1 (CONFIG0[18:17]) after reset.
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

#00 : 0

HXT frequency is lower than from 8 MHz

#01 : 1

HXT frequency is from 8 MHz to 12 MHz

#10 : 2

HXT frequency is from 12 MHz to 16 MHz

#11 : 3

HXT frequency is higher than 16 MHz

End of enumeration elements list.


CLK_CLKSEL0 (CLKSEL0)

Clock Source Select Control Register 0
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKSEL0 CLK_CLKSEL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HCLKSEL STCLKSEL PCLK0SEL PCLK1SEL

HCLKSEL : HCLK Clock Source Selection (Write Protect)\nBefore clock switching, the related clock sources (both pre-select and new-select) must be turned on.\nThe default value is reloaded from the value of CFOSC (CONFIG0[26:24]) in user configuration register of Flash controller by any reset. Therefore the default value is either 000b or 111b.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from HXT clock

#001 : 1

Clock source from LXT clock

#010 : 2

Clock source from PLL clock

#011 : 3

Clock source from LIRC clock

#100 : 4

Clock source from HIRC clock

#101 : 5

Clock source from PLL/2

#111 : 7

Clock source from HIRC/2(24 MHz)

End of enumeration elements list.

STCLKSEL : Cortex-M0 SysTick Clock Source Selection (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 3 - 5 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from HXT clock

#001 : 1

Clock source from LXT clock

#010 : 2

Clock source from HXT/2

#011 : 3

Clock source from HCLK/2

#111 : 7

Clock source from HIRC/4 (12 MHz)

End of enumeration elements list.

PCLK0SEL : PCLK0 Clock Source Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

APB0 BUS clock source from HCLK clock

#1 : 1

APB0 BUS clock source from HCLK/2

End of enumeration elements list.

PCLK1SEL : PCLK1 Clock Source Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

APB1 BUS clock source from HCLK clock

#1 : 1

APB1 BUS clock source from HCLK/2

End of enumeration elements list.


CLK_CLKSEL1 (CLKSEL1)

Clock Source Select Control Register 1
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKSEL1 CLK_CLKSEL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTSEL ADCSEL TMR0SEL TMR1SEL TMR2SEL TMR3SEL UARTSEL BPWM0SEL BPWM1SEL PWM0SEL PWM1SEL

WDTSEL : Watchdog Timer Clock Source Selection (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 0

Reserved

#01 : 1

Clock source from LXT clock

#10 : 2

Clock source from HCLK/2048

#11 : 3

Clock source from LIRC clock

End of enumeration elements list.

ADCSEL : ADC Peripheral Clock Source Selection\n
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source is from HXT clock

#01 : 1

Clock source is from PLL clock

#10 : 2

Clock source is from PCLK0 clock

#11 : 3

Clock source is from HIRC/2 (24 MHz)

End of enumeration elements list.

TMR0SEL : TIMER0 Clock Source Selection\n
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from HXT clock

#001 : 1

Clock source from LXT clock

#010 : 2

Clock source from PCLK0 clock

#011 : 3

Clock source from external clock T0 pin

#101 : 5

Clock source from LIRC clock

#111 : 7

Clock source from HIRC/2 (24 MHz)

End of enumeration elements list.

TMR1SEL : TIMER1 Clock Source Selection\n
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from HXT

#001 : 1

Clock source from LXT

#010 : 2

Clock source from PCLK0

#011 : 3

Clock source from external clock T1 pin

#101 : 5

Clock source from LIRC

#111 : 7

Clock source from HIRC/2 (24 MHz)

End of enumeration elements list.

TMR2SEL : TIMER2 Clock Source Selection\n
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from HXT clock

#001 : 1

Clock source from LXT clock

#010 : 2

Clock source from PCLK1 clock

#011 : 3

Clock source from external clock T2 pin

#101 : 5

Clock source from LIRC clock

#111 : 7

Clock source from HIRC/2 (24 MHz)

End of enumeration elements list.

TMR3SEL : TIMER3 Clock Source Selection\n
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from HXT clock

#001 : 1

Clock source from LXT clock

#010 : 2

Clock source from PCLK1 clock

#011 : 3

Clock source from external clock T3 pin

#101 : 5

Clock source from LIRC clock

#111 : 7

Clock source from HIRC/2 (24 MHz)

End of enumeration elements list.

UARTSEL : UART Clock Source Selection\n
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from HXT clock

#01 : 1

Clock source from PLL clock

#10 : 2

Clock source from LXT clock

#11 : 3

Clock source from HIRC/2 clock

End of enumeration elements list.

BPWM0SEL : BPWM0 Clock Source Selection\nThe peripheral clock source of BPWM0 is defined by BPWM0SEL. \n
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock source from PLL clock

#1 : 1

Clock source from PCLK0 clock

End of enumeration elements list.

BPWM1SEL : BPWM1 Clock Source Selection\nThe peripheral clock source of BPWM1 is defined by BPWM1SEL. \n
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock source from PLL clock

#1 : 1

Clock source from PCLK1 clock

End of enumeration elements list.

PWM0SEL : PWM0 Clock Source Selection\nThe peripheral clock source of PWM1 is defined by PWM0SEL. \n
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock source from PLL clock

#1 : 1

Clock source from PCLK0 clock

End of enumeration elements list.

PWM1SEL : PWM1 Clock Source Selection\nThe peripheral clock source of PWM1 is defined by PWM1SEL. \n
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock source from PLL clock

#1 : 1

Clock source from PCLK1 clock

End of enumeration elements list.


CLK_CLKDIV0 (CLKDIV0)

Clock Divider Number Register 0
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKDIV0 CLK_CLKDIV0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HCLKDIV USBDIV UARTDIV ADCDIV

HCLKDIV : HCLK Clock Divide Number From HCLK Clock Source\n
bits : 0 - 3 (4 bit)
access : read-write

USBDIV : USB Clock Divide Number From PLL Clock\n
bits : 4 - 7 (4 bit)
access : read-write

UARTDIV : UART Clock Divide Number From UART Clock Source\n
bits : 8 - 11 (4 bit)
access : read-write

ADCDIV : ADC Clock Divide Number From EADC Clock Source\n
bits : 16 - 23 (8 bit)
access : read-write


CLK_CLKSEL2 (CLKSEL2)

Clock Source Select Control Register 2
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKSEL2 CLK_CLKSEL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKOSEL WWDTSEL SPI0SEL

CLKOSEL : Clock Divider Clock Source Selection\n
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from HXT clock

#001 : 1

Clock source from LXT clock

#010 : 2

Clock source from HCLK clock

#011 : 3

Clock source from HIRC/2 clock

#101 : 5

Clock source from HIRC clock

#111 : 7

Clock source from SOF (USB Start Of Frame) event. (not 50% duty cycle)

End of enumeration elements list.

WWDTSEL : Window Watchdog Timer Clock Source Selection\n
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

#10 : 2

Clock source from HCLK/2048 clock

#11 : 3

Clock source from LIRC clock

End of enumeration elements list.

SPI0SEL : SPI0 Clock Source Selection\n
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from HXT clock

#01 : 1

Clock source from PLL clock

#10 : 2

Clock source from PCLK0 clock

#11 : 3

Clock source from HIRC clock

End of enumeration elements list.


CLK_PLLCTL (PLLCTL)

PLL Control Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_PLLCTL CLK_PLLCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FBDIV INDIV OUTDIV PD BP OE PLLSRC STBSEL

FBDIV : PLL Feedback Divider Control\nRefer to the formulas below the table.
bits : 0 - 8 (9 bit)
access : read-write

INDIV : PLL Input Divider Control\nRefer to the formulas below the table.
bits : 9 - 13 (5 bit)
access : read-write

OUTDIV : PLL Output Divider Control\nRefer to the formulas below the table.
bits : 14 - 15 (2 bit)
access : read-write

PD : Power-down Mode\nIf set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too.\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

PLL is in normal mode

#1 : 1

PLL is in Power-down mode (default)

End of enumeration elements list.

BP : PLL Bypass Control\n
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

PLL is in normal mode (default)

#1 : 1

PLL clock output is same as PLL input clock FIN

End of enumeration elements list.

OE : PLL OE (FOUT Enable) Pin Control\n
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

PLL FOUT Enabled

#1 : 1

PLL FOUT is fixed low

End of enumeration elements list.

PLLSRC : PLL Source Clock Selection\n
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

PLL source clock from external 4~24 MHz high-speed crystal (HXT)

#1 : 1

PLL source clock from internal 24 MHz high-speed oscillator (HIRC/2)

End of enumeration elements list.

STBSEL : PLL Stable Counter Selection\n
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

PLL stable time is 6144 PLL source clock (suitable for source clock is equal to or less than 12MHz)

#1 : 1

PLL stable time is 12288 PLL source clock (suitable for source clock is larger than 12MHz)

End of enumeration elements list.


CLK_CLKOCTL (CLKOCTL)

Clock Output Control Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKOCTL CLK_CLKOCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FREQSEL CLKOEN DIV1EN

FREQSEL : Clock Output Frequency Selection\nThe formula of output frequency is\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FREQSEL[3:0].
bits : 0 - 3 (4 bit)
access : read-write

CLKOEN : Clock Output Enable Bit\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock Output function Disabled

#1 : 1

Clock Output function Enabled

End of enumeration elements list.

DIV1EN : Clock Output Divide One Enable Bit\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock Output will output clock with source frequency divided by FREQSEL

#1 : 1

Clock Output will output clock with source frequency

End of enumeration elements list.


CLK_APBCLK1 (APBCLK1)

APB Devices Clock Enable Control Register 1
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_APBCLK1 CLK_APBCLK1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USCI0CKEN

USCI0CKEN : USCI0 Clock Enable Bit\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

USCI0 clock Disabled

#1 : 1

USCI0 clock Enabled

End of enumeration elements list.


CLK_CLKSEL3 (CLKSEL3)

Clock Source Select Control Register 3
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKSEL3 CLK_CLKSEL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBDSEL

USBDSEL : USBD Clock Source Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock source from HIRC

#1 : 1

Clock source from PLL clock

End of enumeration elements list.


CLK_AHBCLK (AHBCLK)

AHB Devices Clock Enable Control Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_AHBCLK CLK_AHBCLK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDMACKEN ISPCKEN GPIOACKEN GPIOBCKEN GPIOCCKEN GPIODCKEN GPIOECKEN GPIOFCKEN

PDMACKEN : PDMA Controller Clock Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

PDMA peripheral clock Disabled

#1 : 1

PDMA peripheral clock Enabled

End of enumeration elements list.

ISPCKEN : Flash ISP Controller Clock Enable Bit\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Flash ISP peripheral clock Disabled

#1 : 1

Flash ISP peripheral clock Enabled

End of enumeration elements list.

GPIOACKEN : General Purpose I/O PA Group Clock Enable Bit\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO PA group clock Disabled

#1 : 1

GPIO PA group clock Enabled

End of enumeration elements list.

GPIOBCKEN : General Purpose I/O PB Group Clock Enable Bit\n
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO PB group clock Disabled

#1 : 1

GPIO PB group clock Enabled

End of enumeration elements list.

GPIOCCKEN : General Purpose I/O PC Group Clock Enable Bit\n
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO PC group clock Disabled

#1 : 1

GPIO PC group clock Enabled

End of enumeration elements list.

GPIODCKEN : General Purpose I/O PD Group Clock Enable Bit\n
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO PD group clock Disabled

#1 : 1

GPIO PD group clock Enabled

End of enumeration elements list.

GPIOECKEN : General Purpose I/O PE Group Clock Enable Bit\n
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO PE group clock Disabled

#1 : 1

GPIO PE group clock Enabled

End of enumeration elements list.

GPIOFCKEN : General Purpose I/O PF Group Clock Enable Bit\n
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO PF group clock Disabled

#1 : 1

GPIO PF group clock Enabled

End of enumeration elements list.


CLK_CLKDCTL (CLKDCTL)

Clock Fail Detector Control Register
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKDCTL CLK_CLKDCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HXTFDEN HXTFIEN LXTFDEN LXTFIEN HXTFQDEN HXTFQIEN

HXTFDEN : HXT Clock Fail Detector Enable Bit\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

4~24 MHz external high speed crystal oscillator (HXT) clock Fail detector Disabled

#1 : 1

4~24 MHz external high speed crystal oscillator (HXT) clock Fail detector Enabled

End of enumeration elements list.

HXTFIEN : HXT Clock Fail Interrupt Enable Bit\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

4~24 MHz external high speed crystal oscillator (HXT)clock Fail interrupt Disabled

#1 : 1

4~24 MHz external high speed crystal oscillator (HXT)clock Fail interrupt Enabled

End of enumeration elements list.

LXTFDEN : LXT Clock Fail Detector Enable Bit\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

32.768 kHz external low speed crystal oscillator (LXT) clock Fail detector Disabled

#1 : 1

32.768 kHz external low speed crystal oscillator (LXT) clock Fail detector Enabled

End of enumeration elements list.

LXTFIEN : LXT Clock Fail Interrupt Enable Bit\n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

32.768 kHz external low speed crystal oscillator (LXT) clock Fail interrupt Disabled

#1 : 1

32.768 kHz external low speed crystal oscillator (LXT) clock Fail interrupt Enabled

End of enumeration elements list.

HXTFQDEN : HXT Clock Frequency Monitor Enable Bit\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor Disabled

#1 : 1

4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor Enabled

End of enumeration elements list.

HXTFQIEN : HXT Clock Frequency Monitor Interrupt Enable Bit\n
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor fail interrupt Disabled

#1 : 1

4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor fail interrupt Enabled

End of enumeration elements list.


CLK_CLKDSTS (CLKDSTS)

Clock Fail Detector Status Register
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKDSTS CLK_CLKDSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HXTFIF LXTFIF HXTFQIF

HXTFIF : HXT Clock Fail Interrupt Flag\nNote: Write 1 to clear the bit to 0.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

4~24 MHz external high speed crystal oscillator (HXT) clock normal

#1 : 1

4~24 MHz external high speed crystal oscillator (HXT) clock stop

End of enumeration elements list.

LXTFIF : LXT Clock Fail Interrupt Flag\nNote: Write 1 to clear the bit to 0.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

32.768 kHz external low speed crystal oscillator (LXT) clock normal

#1 : 1

32.768 kHz external low speed crystal oscillator (LXT) stop

End of enumeration elements list.

HXTFQIF : HXT Clock Frequency Monitor Interrupt Flag\nNote: Write 1 to clear the bit to 0.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

4~24 MHz external high speed crystal oscillator (HXT) clock normal

#1 : 1

4~24 MHz external high speed crystal oscillator (HXT) clock frequency abnormal

End of enumeration elements list.


CLK_CDUPB (CDUPB)

Clock Frequency Detector Upper Boundary Register
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CDUPB CLK_CDUPB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UPERBD

UPERBD : HXT Clock Frequency Detector Upper Boundary\nThe bits define the high value of frequency monitor window.\nWhen HXT frequency monitor value higher than this register, the HXT frequency detect fail interrupt flag will set to 1.
bits : 0 - 9 (10 bit)
access : read-write


CLK_CDLOWB (CDLOWB)

Clock Frequency Detector Low Boundary Register
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CDLOWB CLK_CDLOWB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOWERBD

LOWERBD : HXT Clock Frequency Detector Low Boundary\nThe bits define the low value of frequency monitor window.\nWhen HXT frequency monitor value lower than this register, the HXT frequency detect fail interrupt flag will set to 1.
bits : 0 - 9 (10 bit)
access : read-write


CLK_APBCLK0 (APBCLK0)

APB Devices Clock Enable Control Register 0
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_APBCLK0 CLK_APBCLK0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTCKEN TMR0CKEN TMR1CKEN TMR2CKEN TMR3CKEN CLKOCKEN I2C0CKEN I2C1CKEN SPI0CKEN UART0CKEN BPWM0CKEN BPWM1CKEN PWM0CKEN PWM1CKEN USBDCKEN ADCCKEN

WDTCKEN : Watchdog Timer Clock Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Watchdog Timer Clock Disabled

#1 : 1

Watchdog Timer Clock Enabled

End of enumeration elements list.

TMR0CKEN : Timer0 Clock Enable Bit\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer0 Clock Disabled

#1 : 1

Timer0 Clock Enabled

End of enumeration elements list.

TMR1CKEN : Timer1 Clock Enable Bit\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer1 Clock Disabled

#1 : 1

Timer1 Clock Enabled

End of enumeration elements list.

TMR2CKEN : Timer2 Clock Enable Bit\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer2 Clock Disabled

#1 : 1

Timer2 Clock Enabled

End of enumeration elements list.

TMR3CKEN : Timer3 Clock Enable Bit\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer3 Clock Disabled

#1 : 1

Timer3 Clock Enabled

End of enumeration elements list.

CLKOCKEN : CLKO Clock Enable Bit\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

CLKO Clock Disabled

#1 : 1

CLKO Clock Enabled

End of enumeration elements list.

I2C0CKEN : I2C0 Clock Enable Bit\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2C0 Clock Disabled

#1 : 1

I2C0 Clock Enabled

End of enumeration elements list.

I2C1CKEN : I2C1 Clock Enable Bit\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2C1 Clock Disabled

#1 : 1

I2C1 Clock Enabled

End of enumeration elements list.

SPI0CKEN : SPI0 Clock Enable Bit\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI0 Clock Disabled

#1 : 1

SPI0 Clock Enabled

End of enumeration elements list.

UART0CKEN : UART0 Clock Enable Bit\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART0 clock Disabled

#1 : 1

UART0 clock Enabled

End of enumeration elements list.

BPWM0CKEN : BPWM0 Clock Enable Bit\n
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

BPWM0 clock Disabled

#1 : 1

BPWM0 clock Enabled

End of enumeration elements list.

BPWM1CKEN : BPWM1 Clock Enable Bit\n
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

BPWM1 clock Disabled

#1 : 1

BPWM1 clock Enabled

End of enumeration elements list.

PWM0CKEN : PWM0 Clock Enable Bit\n
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM0 clock Disabled

#1 : 1

PWM0 clock Enabled

End of enumeration elements list.

PWM1CKEN : PWM1 Clock Enable Bit\n
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM1 clock Disabled

#1 : 1

PWM1 clock Enabled

End of enumeration elements list.

USBDCKEN : USB Device Clock Enable Bit\n
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

USB Device clock Disabled

#1 : 1

USB Device clock Enabled

End of enumeration elements list.

ADCCKEN : Analog-digital-converter (ADC) Clock Enable Bit\n
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

ADC clock Disabled

#1 : 1

ADC clock Enabled

End of enumeration elements list.


CLK_STATUS (STATUS)

Clock Status Monitor Register
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CLK_STATUS CLK_STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HXTSTB LXTSTB PLLSTB LIRCSTB HIRCSTB CLKSFAIL

HXTSTB : HXT Clock Source Stable Flag (Read Only)\n
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

4~24 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled

#1 : 1

4~24 MHz external high speed crystal oscillator (HXT)clock is stable and enabled

End of enumeration elements list.

LXTSTB : LXT Clock Source Stable Flag (Read Only)\n
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled

#1 : 1

32.768 kHz external low speed crystal oscillator (LXT) clock is stabled and enabled

End of enumeration elements list.

PLLSTB : Internal PLL Clock Source Stable Flag (Read Only)\n
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

Internal PLL clock is not stable or disabled

#1 : 1

Internal PLL clock is stable and enabled

End of enumeration elements list.

LIRCSTB : LIRC Clock Source Stable Flag (Read Only)\n
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

#0 : 0

10 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled

#1 : 1

10 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled

End of enumeration elements list.

HIRCSTB : HIRC Clock Source Stable Flag (Read Only)\n
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

48 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled

#1 : 1

48 MHz internal high speed RC oscillator (HIRC) clock is stabe and enabled

End of enumeration elements list.

CLKSFAIL : Clock Switching Fail Flag (Read Only) \nThis bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1.\nNote 1: Clock switch will finish automatically when target clcok is stable even if this bit already set to 1.
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

#0 : 0

Clock switching success

#1 : 1

Clock switching failure

End of enumeration elements list.



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