\n
address_offset : 0x0 Bytes (0x0)
size : 0x64 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x400 Bytes (0x0)
size : 0x44 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x460 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x480 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
PDMA_DSCT1_FIRST (DSCT1_FIRST)
PDMA_DSCT2_FIRST (DSCT2_FIRST)
PDMA_DSCT3_FIRST (DSCT3_FIRST)
PDMA_DSCT4_FIRST (DSCT4_FIRST)
PDMA_DSCT0_FIRST (DSCT0_FIRST)
Descriptor Table Control Register of PDMA Channel 0
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPMODE : PDMA Operation Mode Selection\nNote: Before filling transfer task in the Descriptor Table, user must check if the descriptor table is complete.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically
#01 : 1
Basic mode: The descriptor table only has one task. When this task is finished, the PDMA_INTSTS[n] will be asserted
#10 : 2
Scatter-Gather mode: When operating in this mode, user must give the first descriptor table address in PDMA_DSCT_FIRST register; PDMA controller will ignore this task, then load the next task to execute
#11 : 3
Reserved
End of enumeration elements list.
TXTYPE : Transfer Type\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Burst transfer type
#1 : 1
Single transfer type
End of enumeration elements list.
BURSIZE : Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type.
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
#000 : 0
128 Transfers
#001 : 1
64 Transfers
#010 : 2
32 Transfers
#011 : 3
16 Transfers
#100 : 4
8 Transfers
#101 : 5
4 Transfers
#110 : 6
2 Transfers
#111 : 7
1 Transfers
End of enumeration elements list.
TBINTDIS : Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is set when PDMA controller finishes transfer task, it will not generates interrupt. \nNote: If this bit set to '1', the TEMPTYF will not be set.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Table interrupt Enabled
#1 : 1
Table interrupt Disabled
End of enumeration elements list.
SAINC : Source Address Increment\nThis field is used to set the source address increment size.\n
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#11 : 3
No increment (fixed address)
End of enumeration elements list.
DAINC : Destination Address Increment\nThis field is used to set the destination address increment size.\n
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#11 : 3
No increment (fixed address)
End of enumeration elements list.
TXWIDTH : Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 0
One byte (8 bit) is transferred for every operation
#01 : 1
One half-word (16 bit) is transferred for every operation
#10 : 2
One word (32-bit) is transferred for every operation
#11 : 3
Reserved
End of enumeration elements list.
TXCNT : Transfer Count\nThe TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1); The maximum transfer count is 16384, every transfer may be byte, half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA finish each transfer data, this field will be decrease immediately.
bits : 16 - 29 (14 bit)
access : read-write
Descriptor Table Control Register of PDMA Channel 1
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Source Address Register of PDMA Channel 1
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Address Register of PDMA Channel 1
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
First Scatter-gather Descriptor Table Offset of PDMA Channel 1
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Descriptor Table Control Register of PDMA Channel 2
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Source Address Register of PDMA Channel 2
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Address Register of PDMA Channel 2
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
First Scatter-gather Descriptor Table Offset of PDMA Channel 2
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Descriptor Table Control Register of PDMA Channel 3
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Source Address Register of PDMA Channel 3
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Address Register of PDMA Channel 3
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
First Scatter-gather Descriptor Table Offset of PDMA Channel 3
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Source Address Register of PDMA Channel 0
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SA : PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA controller.
bits : 0 - 31 (32 bit)
access : read-write
Descriptor Table Control Register of PDMA Channel 4
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMA Channel Control Register
address_offset : 0x400 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN0 : PDMA Channel N Enable Bit\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel [n] Disabled
#1 : 1
PDMA channel [n] Enabled
End of enumeration elements list.
CHEN1 : PDMA Channel N Enable Bit\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel [n] Disabled
#1 : 1
PDMA channel [n] Enabled
End of enumeration elements list.
CHEN2 : PDMA Channel N Enable Bit\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel [n] Disabled
#1 : 1
PDMA channel [n] Enabled
End of enumeration elements list.
CHEN3 : PDMA Channel N Enable Bit\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel [n] Disabled
#1 : 1
PDMA channel [n] Enabled
End of enumeration elements list.
CHEN4 : PDMA Channel N Enable Bit\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel [n] Disabled
#1 : 1
PDMA channel [n] Enabled
End of enumeration elements list.
PDMA Transfer Pause Control Register
address_offset : 0x404 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
PAUSE0 : PDMA Channel N Transfer Pause Control Register (Write Only)\nUser can set PAUSEn bit field to pause the PDMA transfer.\n
bits : 0 - 0 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Pause PDMA channel n transfer. When user sets PDMA_PAUSE bit, the operation will pause the on-going transfer, but not finish the rest of transfers, and then clear the channel enable bit (PDMA_CHCTL [CHEN]) and clear request active flag. If re-enable the paused channel agian, the remaining transfers will be processed
End of enumeration elements list.
PAUSE1 : PDMA Channel N Transfer Pause Control Register (Write Only)\nUser can set PAUSEn bit field to pause the PDMA transfer.\n
bits : 1 - 1 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Pause PDMA channel n transfer. When user sets PDMA_PAUSE bit, the operation will pause the on-going transfer, but not finish the rest of transfers, and then clear the channel enable bit (PDMA_CHCTL [CHEN]) and clear request active flag. If re-enable the paused channel agian, the remaining transfers will be processed
End of enumeration elements list.
PAUSE2 : PDMA Channel N Transfer Pause Control Register (Write Only)\nUser can set PAUSEn bit field to pause the PDMA transfer.\n
bits : 2 - 2 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Pause PDMA channel n transfer. When user sets PDMA_PAUSE bit, the operation will pause the on-going transfer, but not finish the rest of transfers, and then clear the channel enable bit (PDMA_CHCTL [CHEN]) and clear request active flag. If re-enable the paused channel agian, the remaining transfers will be processed
End of enumeration elements list.
PAUSE3 : PDMA Channel N Transfer Pause Control Register (Write Only)\nUser can set PAUSEn bit field to pause the PDMA transfer.\n
bits : 3 - 3 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Pause PDMA channel n transfer. When user sets PDMA_PAUSE bit, the operation will pause the on-going transfer, but not finish the rest of transfers, and then clear the channel enable bit (PDMA_CHCTL [CHEN]) and clear request active flag. If re-enable the paused channel agian, the remaining transfers will be processed
End of enumeration elements list.
PAUSE4 : PDMA Channel N Transfer Pause Control Register (Write Only)\nUser can set PAUSEn bit field to pause the PDMA transfer.\n
bits : 4 - 4 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Pause PDMA channel n transfer. When user sets PDMA_PAUSE bit, the operation will pause the on-going transfer, but not finish the rest of transfers, and then clear the channel enable bit (PDMA_CHCTL [CHEN]) and clear request active flag. If re-enable the paused channel agian, the remaining transfers will be processed
End of enumeration elements list.
PDMA Software Request Register
address_offset : 0x408 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SWREQ0 : PDMA Channel N Software Request Register (Write Only)\nSet this bit to 1 to generate a software request to PDMA channel n.\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 0 - 0 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Generate a software request
End of enumeration elements list.
SWREQ1 : PDMA Channel N Software Request Register (Write Only)\nSet this bit to 1 to generate a software request to PDMA channel n.\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 1 - 1 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Generate a software request
End of enumeration elements list.
SWREQ2 : PDMA Channel N Software Request Register (Write Only)\nSet this bit to 1 to generate a software request to PDMA channel n.\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 2 - 2 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Generate a software request
End of enumeration elements list.
SWREQ3 : PDMA Channel N Software Request Register (Write Only)\nSet this bit to 1 to generate a software request to PDMA channel n.\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 3 - 3 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Generate a software request
End of enumeration elements list.
SWREQ4 : PDMA Channel N Software Request Register (Write Only)\nSet this bit to 1 to generate a software request to PDMA channel n.\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 4 - 4 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Generate a software request
End of enumeration elements list.
PDMA Channel Request Status Register
address_offset : 0x40C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
REQSTS0 : PDMA Channel N Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_RESET register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA Channel n has no request
#1 : 1
PDMA Channel n has a request
End of enumeration elements list.
REQSTS1 : PDMA Channel N Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_RESET register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA Channel n has no request
#1 : 1
PDMA Channel n has a request
End of enumeration elements list.
REQSTS2 : PDMA Channel N Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_RESET register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA Channel n has no request
#1 : 1
PDMA Channel n has a request
End of enumeration elements list.
REQSTS3 : PDMA Channel N Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_RESET register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA Channel n has no request
#1 : 1
PDMA Channel n has a request
End of enumeration elements list.
REQSTS4 : PDMA Channel N Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_RESET register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA Channel n has no request
#1 : 1
PDMA Channel n has a request
End of enumeration elements list.
PDMA Fixed Priority Setting Register
address_offset : 0x410 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPRISET0 : PDMA Channel N Fixed Priority Setting Register\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, user should use PDMA_PRICLR register to clear fixed priority.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nCorresponding PDMA channel is round-robin priority
#1 : 1
Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority
End of enumeration elements list.
FPRISET1 : PDMA Channel N Fixed Priority Setting Register\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, user should use PDMA_PRICLR register to clear fixed priority.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nCorresponding PDMA channel is round-robin priority
#1 : 1
Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority
End of enumeration elements list.
FPRISET2 : PDMA Channel N Fixed Priority Setting Register\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, user should use PDMA_PRICLR register to clear fixed priority.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nCorresponding PDMA channel is round-robin priority
#1 : 1
Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority
End of enumeration elements list.
FPRISET3 : PDMA Channel N Fixed Priority Setting Register\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, user should use PDMA_PRICLR register to clear fixed priority.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nCorresponding PDMA channel is round-robin priority
#1 : 1
Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority
End of enumeration elements list.
FPRISET4 : PDMA Channel N Fixed Priority Setting Register\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, user should use PDMA_PRICLR register to clear fixed priority.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nCorresponding PDMA channel is round-robin priority
#1 : 1
Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority
End of enumeration elements list.
PDMA Fixed Priority Clear Register
address_offset : 0x414 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FPRICLR0 : PDMA Channel N Fixed Priority Clear Register (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
bits : 0 - 0 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Clear PDMA channel [n] fixed priority setting
End of enumeration elements list.
FPRICLR1 : PDMA Channel N Fixed Priority Clear Register (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
bits : 1 - 1 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Clear PDMA channel [n] fixed priority setting
End of enumeration elements list.
FPRICLR2 : PDMA Channel N Fixed Priority Clear Register (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
bits : 2 - 2 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Clear PDMA channel [n] fixed priority setting
End of enumeration elements list.
FPRICLR3 : PDMA Channel N Fixed Priority Clear Register (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
bits : 3 - 3 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Clear PDMA channel [n] fixed priority setting
End of enumeration elements list.
FPRICLR4 : PDMA Channel N Fixed Priority Clear Register (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
bits : 4 - 4 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Clear PDMA channel [n] fixed priority setting
End of enumeration elements list.
PDMA Interrupt Enable Register
address_offset : 0x418 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTEN0 : PDMA Channel N Interrupt Enable Register\nThis field is used for enabling PDMA channel[n] interrupt.\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel n interrupt Disabled
#1 : 1
PDMA channel n interrupt Enabled
End of enumeration elements list.
INTEN1 : PDMA Channel N Interrupt Enable Register\nThis field is used for enabling PDMA channel[n] interrupt.\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel n interrupt Disabled
#1 : 1
PDMA channel n interrupt Enabled
End of enumeration elements list.
INTEN2 : PDMA Channel N Interrupt Enable Register\nThis field is used for enabling PDMA channel[n] interrupt.\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel n interrupt Disabled
#1 : 1
PDMA channel n interrupt Enabled
End of enumeration elements list.
INTEN3 : PDMA Channel N Interrupt Enable Register\nThis field is used for enabling PDMA channel[n] interrupt.\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel n interrupt Disabled
#1 : 1
PDMA channel n interrupt Enabled
End of enumeration elements list.
INTEN4 : PDMA Channel N Interrupt Enable Register\nThis field is used for enabling PDMA channel[n] interrupt.\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel n interrupt Disabled
#1 : 1
PDMA channel n interrupt Enabled
End of enumeration elements list.
PDMA Interrupt Status Register
address_offset : 0x41C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ABTIF : PDMA Read/Write Target Abort Interrupt Flag (Read-only)\nThis bit indicates that PDMA has target abort error; Software can read PDMA_ABTSTS register to find which channel has target abort error.\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AHB bus ERROR response received
#1 : 1
AHB bus ERROR response received
End of enumeration elements list.
TDIF : Transfer Done Interrupt Flag (Read Only)\nThis bit indicates that PDMA controller has finished transmission; User can read PDMA_TDSTS register to indicate which channel finished transfer.\n
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Not finished yet
#1 : 1
PDMA channel has finished transmission
End of enumeration elements list.
TEIF : Table Empty Interrupt Flag (Read Only)\nThis bit indicates PDMA channel scatter-gather table is empty. User can read PDMA_SCATSTS register to indicate which channel scatter-gather table is empty.\n
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA channel scatter-gather table is not empty
#1 : 1
PDMA channel scatter-gather table is empty
End of enumeration elements list.
REQTOF0 : PDMA Channel N Request Time-out Flag\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOCn, user can write 1 to clear these bits.\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No request time-out
#1 : 1
Peripheral request time-out
End of enumeration elements list.
REQTOF1 : PDMA Channel N Request Time-out Flag\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOCn, user can write 1 to clear these bits.\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
No request time-out
#1 : 1
Peripheral request time-out
End of enumeration elements list.
PDMA Channel Read/Write Target Abort Flag Register
address_offset : 0x420 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ABTIF0 : PDMA Channel N Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error or transfer source and destination address not alignment; User can write 1 to clear these bits. \n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AHB bus ERROR response received when channel n transfer
#1 : 1
AHB bus ERROR response received when channel n transfer
End of enumeration elements list.
ABTIF1 : PDMA Channel N Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error or transfer source and destination address not alignment; User can write 1 to clear these bits. \n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AHB bus ERROR response received when channel n transfer
#1 : 1
AHB bus ERROR response received when channel n transfer
End of enumeration elements list.
ABTIF2 : PDMA Channel N Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error or transfer source and destination address not alignment; User can write 1 to clear these bits. \n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AHB bus ERROR response received when channel n transfer
#1 : 1
AHB bus ERROR response received when channel n transfer
End of enumeration elements list.
ABTIF3 : PDMA Channel N Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error or transfer source and destination address not alignment; User can write 1 to clear these bits. \n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AHB bus ERROR response received when channel n transfer
#1 : 1
AHB bus ERROR response received when channel n transfer
End of enumeration elements list.
ABTIF4 : PDMA Channel N Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error or transfer source and destination address not alignment; User can write 1 to clear these bits. \n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AHB bus ERROR response received when channel n transfer
#1 : 1
AHB bus ERROR response received when channel n transfer
End of enumeration elements list.
PDMA Channel Transfer Done Flag Register
address_offset : 0x424 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDIF0 : PDMA Channel N Transfer Done Flag Register\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel transfer has not finished
#1 : 1
PDMA channel has finished transmission
End of enumeration elements list.
TDIF1 : PDMA Channel N Transfer Done Flag Register\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel transfer has not finished
#1 : 1
PDMA channel has finished transmission
End of enumeration elements list.
TDIF2 : PDMA Channel N Transfer Done Flag Register\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel transfer has not finished
#1 : 1
PDMA channel has finished transmission
End of enumeration elements list.
TDIF3 : PDMA Channel N Transfer Done Flag Register\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel transfer has not finished
#1 : 1
PDMA channel has finished transmission
End of enumeration elements list.
TDIF4 : PDMA Channel N Transfer Done Flag Register\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel transfer has not finished
#1 : 1
PDMA channel has finished transmission
End of enumeration elements list.
PDMA Scatter-gather Table Empty Status Register
address_offset : 0x428 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TEMPTYFn : Table Empty Flag Register\nThis bit indicates which PDMA channel table is empty when channel has a request, no matter request from software or peripheral, but operation mode of channel descriptor table is idle mode, or channel has finished current transfer and next table operation mode is idle mode for PDMA Scatter-Gather mode. User can write 1 to clear these bits.\n
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : 0
PDMA channel scatter-gather table is not empty
1 : 1
PDMA channel scatter-gather table is empty
End of enumeration elements list.
PDMA Transfer Active Flag Register
address_offset : 0x42C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXACTF0 : PDMA Channel N Transfer on Active Flag Register (Read Only)\nThis bit indicates which PDMA channel is in active.\n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA channel is not finished
#1 : 1
PDMA channel is active
End of enumeration elements list.
TXACTF1 : PDMA Channel N Transfer on Active Flag Register (Read Only)\nThis bit indicates which PDMA channel is in active.\n
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA channel is not finished
#1 : 1
PDMA channel is active
End of enumeration elements list.
TXACTF2 : PDMA Channel N Transfer on Active Flag Register (Read Only)\nThis bit indicates which PDMA channel is in active.\n
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA channel is not finished
#1 : 1
PDMA channel is active
End of enumeration elements list.
TXACTF3 : PDMA Channel N Transfer on Active Flag Register (Read Only)\nThis bit indicates which PDMA channel is in active.\n
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA channel is not finished
#1 : 1
PDMA channel is active
End of enumeration elements list.
TXACTF4 : PDMA Channel N Transfer on Active Flag Register (Read Only)\nThis bit indicates which PDMA channel is in active.\n
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA channel is not finished
#1 : 1
PDMA channel is active
End of enumeration elements list.
PDMA Time-out Prescaler Register
address_offset : 0x430 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOUTPSC0 : PDMA Channel 0 Time-out Clock Source Prescaler Bits\n
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
PDMA channel 0 time-out clock source is HCLK/28
#001 : 1
PDMA channel 0 time-out clock source is HCLK/29
#010 : 2
PDMA channel 0 time-out clock source is HCLK/210
#011 : 3
PDMA channel 0 time-out clock source is HCLK/211
#100 : 4
PDMA channel 0 time-out clock source is HCLK/212
#101 : 5
PDMA channel 0 time-out clock source is HCLK/213
#110 : 6
PDMA channel 0 time-out clock source is HCLK/214
#111 : 7
PDMA channel 0 time-out clock source is HCLK/215
End of enumeration elements list.
TOUTPSC1 : PDMA Channel 1 Time-out Clock Source Prescaler Bits\n
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
#000 : 0
PDMA channel 1 time-out clock source is HCLK/28
#001 : 1
PDMA channel 1 time-out clock source is HCLK/29
#010 : 2
PDMA channel 1 time-out clock source is HCLK/210
#011 : 3
PDMA channel 1 time-out clock source is HCLK/211
#100 : 4
PDMA channel 1 time-out clock source is HCLK/212
#101 : 5
PDMA channel 1 time-out clock source is HCLK/213
#110 : 6
PDMA channel 1 time-out clock source is HCLK/214
#111 : 7
PDMA channel 1 time-out clock source is HCLK/215
End of enumeration elements list.
PDMA Time-out Enable Register
address_offset : 0x434 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOUTEN0 : PDMA Channel 0 Time-out Enable Bit\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA Channel 0 time-out function Disable
#1 : 1
PDMA Channel 0 time-out function Enable
End of enumeration elements list.
TOUTEN1 : PDMA Channel 1 Time-out Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA Channel 1 time-out function Disable
#1 : 1
PDMA Channel 1 time-out function Enable
End of enumeration elements list.
PDMA Time-out Interrupt Enable Register
address_offset : 0x438 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOUTIEN0 : PDMA Channel 0 Time-out Interrupt Enable Bit\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA Channel 0 time-out interrupt Disable
#1 : 1
PDMA Channel 0 time-out interrupt Enable
End of enumeration elements list.
TOUTIEN1 : PDMA Channel 1 Time-out Interrupt Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA Channel 1 time-out interrupt Disable
#1 : 1
PDMA Channel 1 time-out interrupt Enable
End of enumeration elements list.
PDMA Scatter-gather Descriptor Table Base Address Register
address_offset : 0x43C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCATBA : PDMA Scatter-gather Descriptor Table Address Register\nIn Scatter-Gather mode, this is the base address for calculating the next link - list address. The next link address equation is \nNote: Only useful in Scatter-Gather mode.
bits : 16 - 31 (16 bit)
access : read-write
Source Address Register of PDMA Channel 4
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMA Channel 0 and Channel 1 Time-out Counter Register
address_offset : 0x440 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOC0 : Time-out Counter for Channel 0\nThis controls the period of time-out function for channel 0. The calculation unit is based on TOUTPSC0 (PDMA_TOUTPSC[2:0]) clock.\n
bits : 0 - 15 (16 bit)
access : read-write
TOC1 : Time-out Counter for Channel 1\nThis controls the period of time-out function for channel 1. The calculation unit is based on TOUTPSC1 (PDMA_TOUTPSC[6:4]) clock. The example of time-out period can refer TOC0 bit description.
bits : 16 - 31 (16 bit)
access : read-write
PDMA Channel Reset Control Register
address_offset : 0x460 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESET0 : PDMA Channel N Reset Control Register \nUser can set this bit field to reset the PDMA channel.\nNote: This bit will be cleared automatically after finishing reset process.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset PDMA channel n. When user sets PDMA_RESET bit, the operation will finish the on-going transfer and then clear the channel enable bit (PDMA_CHCTL [CHEN]) and clear request active flag. If re-enable channel after channel reset, PDMA will re-load the channel description table to execute PDMA task
End of enumeration elements list.
RESET1 : PDMA Channel N Reset Control Register \nUser can set this bit field to reset the PDMA channel.\nNote: This bit will be cleared automatically after finishing reset process.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset PDMA channel n. When user sets PDMA_RESET bit, the operation will finish the on-going transfer and then clear the channel enable bit (PDMA_CHCTL [CHEN]) and clear request active flag. If re-enable channel after channel reset, PDMA will re-load the channel description table to execute PDMA task
End of enumeration elements list.
RESET2 : PDMA Channel N Reset Control Register \nUser can set this bit field to reset the PDMA channel.\nNote: This bit will be cleared automatically after finishing reset process.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset PDMA channel n. When user sets PDMA_RESET bit, the operation will finish the on-going transfer and then clear the channel enable bit (PDMA_CHCTL [CHEN]) and clear request active flag. If re-enable channel after channel reset, PDMA will re-load the channel description table to execute PDMA task
End of enumeration elements list.
RESET3 : PDMA Channel N Reset Control Register \nUser can set this bit field to reset the PDMA channel.\nNote: This bit will be cleared automatically after finishing reset process.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset PDMA channel n. When user sets PDMA_RESET bit, the operation will finish the on-going transfer and then clear the channel enable bit (PDMA_CHCTL [CHEN]) and clear request active flag. If re-enable channel after channel reset, PDMA will re-load the channel description table to execute PDMA task
End of enumeration elements list.
RESET4 : PDMA Channel N Reset Control Register \nUser can set this bit field to reset the PDMA channel.\nNote: This bit will be cleared automatically after finishing reset process.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset PDMA channel n. When user sets PDMA_RESET bit, the operation will finish the on-going transfer and then clear the channel enable bit (PDMA_CHCTL [CHEN]) and clear request active flag. If re-enable channel after channel reset, PDMA will re-load the channel description table to execute PDMA task
End of enumeration elements list.
Destination Address Register of PDMA Channel 4
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMA Channel 0 to Channel 3 Request Source Select Register
address_offset : 0x480 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REQSRC0 : Channel 0 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 0. User can configure the peripheral by setting REQSRC0.\nNote 1: A peripheral can't assign to two channels at the same time.\nNote 2: This field is useless when transfer between memory and memory.
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : 0
Disable PDMA peripheral request
1 : 1
reserved
4 : 4
Channel connects to UART_TX
5 : 5
Channel connects to UART_RX
6 : 6
Reserved
7 : 7
Reserved
8 : 8
Reserved
9 : 9
Reserved
10 : 10
Channel connects to USCI_TX
11 : 11
Channel connects to USCI_RX
12 : 12
Reserved
13 : 13
Reserved
14 : 14
Reserved
15 : 15
Reserved
16 : 16
Channel connects to SPI_TX
17 : 17
Channel connects to SPI_RX
18 : 18
Reserved
19 : 19
Reserved
20 : 20
Channel connects to ADC_RX
21 : 21
Channel connects to PWM0_P0_RX
22 : 22
Channel connects to PWM0_P1_RX
23 : 23
Channel connects to PWM0_P2_RX
24 : 24
Channel connects to PWM1_P0_RX
25 : 25
Channel connects to PWM1_P1_RX
26 : 26
Channel connects to PWM1_P2_RX
27 : 27
Reserved
28 : 28
Channel connects to I2C0_TX
29 : 29
Channel connects to I2C0_RX
30 : 30
Channel connects to I2C1_TX
31 : 31
Channel connects to I2C1_RX
32 : 32
Channel connects to TMR0
33 : 33
Channel connects to TMR1
34 : 34
Channel connects to TMR2
35 : 35
Channel connects to TMR3
End of enumeration elements list.
REQSRC1 : Channel 1 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 1. User can configure the peripheral setting by REQSRC1. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 8 - 13 (6 bit)
access : read-write
REQSRC2 : Channel 2 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 2. User can configure the peripheral setting by REQSRC2. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 16 - 21 (6 bit)
access : read-write
REQSRC3 : Channel 3 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 3. User can configure the peripheral setting by REQSRC3. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 24 - 29 (6 bit)
access : read-write
PDMA Channel 4 Request Source Select Register
address_offset : 0x484 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REQSRC4 : Channel 4 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 4. User can configure the peripheral setting by REQSRC4. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 0 - 5 (6 bit)
access : read-write
First Scatter-gather Descriptor Table Offset of PDMA Channel 4
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Current Scatter-gather Descriptor Table Address of PDMA Channel 0
address_offset : 0x50 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CURADDR : PDMA Current Description Address Register (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and only used for Scatter-Gather mode to indicate the current external description address.
bits : 0 - 31 (32 bit)
access : read-only
Current Scatter-gather Descriptor Table Address of PDMA Channel 1
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Current Scatter-gather Descriptor Table Address of PDMA Channel 2
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Current Scatter-gather Descriptor Table Address of PDMA Channel 3
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Current Scatter-gather Descriptor Table Address of PDMA Channel 4
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Address Register of PDMA Channel 0
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DA : PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA controller.
bits : 0 - 31 (32 bit)
access : read-write
First Scatter-gather Descriptor Table Offset of PDMA Channel 0
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIRST : PDMA First Descriptor Table Offset\nThis field indicates the offset of the first descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA), and the first descriptor table is start from 0x2000_0100, then this field must fill in 0x0100.\nRead Operation:\nWhen operating in scatter-gather mode, the last two bits FIRST[1:0] will become reserved.\nNote1: The first descriptor table address must be word boundary.\nNote2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete.
bits : 0 - 15 (16 bit)
access : read-write
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