\n
address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected
Timer2 Control and Status Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSC : Prescale Counter\n
bits : 0 - 7 (8 bit)
access : read-write
TRGPDMA : Trigger PDMA Enable Bit\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can trigger PDMA.\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer interrupt trigger PDMA Disabled
#1 : 1
Timer interrupt trigger PDMA Enabled
End of enumeration elements list.
TRGBPWM : Trigger BPWM Enable Bit\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can trigger BPWM.\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer interrupt trigger BPWM Disabled
#1 : 1
Timer interrupt trigger BPWM Enabled
End of enumeration elements list.
TRGSSEL : Trigger Source Select Bit\nThis bit is used to select trigger source from Timer time-out interrupt signal or capture interrupt signal.\n
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer time-out interrupt signal is used to trigger PWM, BPWM, PDMA,ADC and DAC
#1 : 1
Capture interrupt signal is used to trigger PWM, BPWM, PDMA, ADC and DAC
End of enumeration elements list.
TRGPWM : Trigger PWM Enable Bit\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can trigger PWM.\n
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer interrupt trigger PWM Disabled
#1 : 1
Timer interrupt trigger PWM Enabled
End of enumeration elements list.
TRGDAC : Trigger DAC Enable Bit\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can trigger DAC.\n
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer interrupt trigger DAC Disabled
#1 : 1
Timer interrupt trigger DAC Enabled
End of enumeration elements list.
TRGADC : Trigger ADC Enable Bit\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can trigger ADC.\n
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer interrupt trigger ADC Disabled
#1 : 1
Timer interrupt trigger ADC Enabled
End of enumeration elements list.
TGLPINSEL : Toggle-output Pin Select\n
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Toggle mode output to Tx (Timer Event Counter Pin)
#1 : 1
Toggle mode output to Tx_EXT (Timer External Capture Pin)
End of enumeration elements list.
WKEN : Wake-up Function Enable Bit\nIf this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.\n
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Wake-up function Disabled if timer interrupt signal generated
#1 : 1
Wake-up function Enabled if timer interrupt signal generated
End of enumeration elements list.
EXTCNTEN : Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. \nNote: When timer is used as an event counter, this bit should be set to 1 and select PCLK as timer clock source.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Event counter mode Disabled
#1 : 1
Event counter mode Enabled
End of enumeration elements list.
ACTSTS : Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\n
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
#0 : 0
24-bit up counter is not active
#1 : 1
24-bit up counter is active
End of enumeration elements list.
RSTCNT : Timer Counter Reset Bit\nSetting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.\n
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset internal 8-bit prescale counter, 24-bit up counter value and CNTEN bit
End of enumeration elements list.
OPMODE : Timer Operating Mode Select\n
bits : 27 - 28 (2 bit)
access : read-write
Enumeration:
#00 : 0
The Timer controller is operated in One-shot mode
#01 : 1
The Timer controller is operated in Periodic mode
#10 : 2
The Timer controller is operated in Toggle-output mode
#11 : 3
The Timer controller is operated in Continuous Counting mode
End of enumeration elements list.
INTEN : Timer Interrupt Enable Bit\nNote: If this bit is enabled, when the timer interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer Interrupt Disabled
#1 : 1
Timer Interrupt Enabled
End of enumeration elements list.
CNTEN : Timer Counting Enable Bit\n
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Stops/Suspends counting
#1 : 1
Starts counting
End of enumeration elements list.
ICEDEBUG : ICE Debug Mode Acknowledge Disable (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
ICE debug mode acknowledgement affects TIMER counting
#1 : 1
ICE debug mode acknowledgement Disabled
End of enumeration elements list.
Timer2 Capture Data Register
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAPDAT : Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on Tx_EXT pin is matched with the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.
bits : 0 - 23 (24 bit)
access : read-only
Timer2 External Control Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTPHASE : Timer External Count Phase \n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
A Falling edge of external counting pin will be counted
#1 : 1
A Rising edge of external counting pin will be counted
End of enumeration elements list.
CAPEDGE : Timer External Capture Pin Edge Detect\n
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
#00 : 0
A Falling edge on Tx_EXT (x= 0~3) pin will be detected
#01 : 1
A Rising edge on Tx_EXT (x= 0~3) pin will be detected
#10 : 2
Either Rising or Falling edge on Tx_EXT (x= 0~3) pin will be detected
#11 : 3
Reserved
End of enumeration elements list.
CAPEN : Timer External Capture Pin Enable \nThis bit enables the Tx_EXT pin. \n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tx_EXT (x= 0~3) pin Disabled
#1 : 1
Tx_EXT (x= 0~3) pin Enabled
End of enumeration elements list.
CAPFUNCS : Capture Function Selection\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
External Capture Mode Enabled
#1 : 1
External Reset Mode Enabled
End of enumeration elements list.
CAPIEN : Timer External Capture Interrupt Enable Bit\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tx_EXT (x= 0~3) pin detection Interrupt Disabled
#1 : 1
Tx_EXT (x= 0~3) pin detection Interrupt Enabled
End of enumeration elements list.
CAPDBEN : Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled, the edge detection of Tx_EXT pin is detected with de-bounce circuit.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tx_EXT (x= 0~3) pin de-bounce Disabled
#1 : 1
Tx_EXT (x= 0~3) pin de-bounce Enabled
End of enumeration elements list.
CNTDBEN : Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled, the edge detection of Tx pin is detected with de-bounce circuit.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tx (x= 0~3) pin de-bounce Disabled
#1 : 1
Tx (x= 0~3) pin de-bounce Enabled
End of enumeration elements list.
Timer2 External Interrupt Status Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPIF : Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tx_EXT (x= 0~3) pin interrupt did not occur
#1 : 1
Tx_EXT (x= 0~3) pin interrupt occurred
End of enumeration elements list.
Timer3 Control and Status Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer3 Compare Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer3 Interrupt Status Register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer3 Data Register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer3 Capture Data Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer3 External Control Register
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer3 External Interrupt Status Register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer2 Compare Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPDAT : Timer Compared Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.\nNote1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field.
bits : 0 - 23 (24 bit)
access : read-write
Timer2 Interrupt Status Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIF : Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
CNT value matches the CMPDAT value
End of enumeration elements list.
TWKF : Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer does not cause CPU wake-up
#1 : 1
CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated
End of enumeration elements list.
Timer2 Data Register
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : Timer Data Register\nIf EXTCNTEN (TIMERx_CTL[24] ) is 0, user can read CNT value to get current 24- bit counter value .\nIf EXTCNTEN (TIMERx_CTL[24] ) is 1, user can read CNT value to get current 24- bit event input counter value.
bits : 0 - 23 (24 bit)
access : read-only
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